ISL6228_14 Datasheet, PDF (11/16 Pages) Intersil Corporation – High-Performance Dual-Output Buck Controller for Notebook Applications

ISL6228
Programming the PWM Switching Frequency
The ISL6228 does not use a clock signal to produce PWMs.
The PWM switching frequency f_SW is programmed by the
resistor R_FSET that is connected from the FSET pin to the
GND pin. The approximate PWM switching frequency is
written as Equation 10:
f_SW
=
-------------¹--------------
K ⋅ R_FSET
(EQ. 10)
Estimating the value of R_FSET is written as Equation 11:
R_FSET
=
--------¹---------
K • f_SW
(EQ. 11)
Where:
- f_SW is the PWM switching frequency
- R_FSET is the f_SW programming resistor
- K = 1.5 x 10^-10
It is recommended that whenever the control loop
compensation network is modified, f_SW should be checked
for the correct frequency and if necessary, adjust R_FSET.
Compensation Design
Figure 6 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C_INT is a 100pF capacitor
integrated inside the IC, connecting across the FB pin and the
COMP signal. R_TOP, R_FB, C_FB and C_INT form the Type-II
compensator. The frequency domain transfer function is given
by Equation 12:
G_COMP(s)
=
-----------¹-----+-----^s----^•--⁽---^R----^T----^O-----^P-----+----^R-----^F----^B----⁾--^•---^C-----^F---^B-------------
s • R_TOP • C_INT • (1 + s • R_FB • C_FB)
(EQ. 12)
C_INT = 100pF
R_FB
C_FB
R_TOP
-
VO
FB
COMP
EA
+
R_BOTTOM
REF
ISL6228
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R³ modulator used in the
ISL6228 makes the LC output filter resemble a first order
system in which the closed loop stability can be achieved with
the recommended Type-II compensation network. Intersil
provides a PC-based tool (example page is shown later) that
can be used to calculate compensation network component
values and help simulate the loop frequency response.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 13:
D
=
-^V-----^O---
V_IN
(EQ. 13)
The output inductor peak-to-peak ripple current is written as
Equation 14:
I_PP
=
V_-----O-----•_--(_---1_{-----–----}D_-----)
f_SW • L
(EQ. 14)
A typical step-down DC/DC converter will have an I_P-P of
20% to 40% of the maximum DC output load current. The
value of I_PP is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 15:
P_COPPER = I_LOAD2 • DCR
(EQ. 15)
Where I_LOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance C_O
into which ripple current I_P-P can flow. Current I_PP develops
a corresponding ripple voltage V_P-P across C_O, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are written as
Equation 16:
ΔV_ESR = I_P-P • ESR
(EQ. 16)
and Equation 17:
ΔV_C
=
----------^I--^P----^---^P-----------
8 • C_O • f_SW
(EQ. 17)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V_P-P is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered. A capacitor
11
FN9095.2
May 7, 2008