ISL6115A Datasheet, PDF (8/10 Pages) Intersil Corporation – 12V Power Distribution Controllers

ISL6115A
Typical Performance Curves (Continued)
ILOAD
ILOAD
GATE
CTIM
VOUT
CTIM
GATE
VOUT
FIGURE 12. IOC REGULATION and TURN-OFF
ISL6115AEVAL1Z Board
The ISL6115AEVAL1Z is default provided as a +12V high
side switch controller with the CR level set at ~2.5A. See
Figure 11 for ISL6115AEVAL1Z schematic and Table 3 for
BOM. Bias and load connection points are provided along
with test points for each IC pin.
With J1 installed the ISL6115A will be biased from the +12V
supply (V_IN) being switched. Connect the load to VLOAD+.
PWRON pin pulls high internally enabling the ISL6115A if
not driven low via PWRON test point or J2.
VLOAD+
AGND
VOUT
R3
R1
U1
R2
C1
VIN
1
8
2 _ISL6115A 7
3
U2
6
4
5
C2
J2
PWRON
PGOOD
C_TIM
C3
R4
J1
+12V
V_BIAS
V_BIAS
FIGURE 13. WOC TURN-OFF and RESTART
With R₃ = 1.24kΩ the CR Vth is set to 24.8mV and with the
10mΩ sense resistor (R₁) the ISL6115AEVAL1Z has a
nominal CR level of 2.5~A. The 0.01µF delay time to
latch-off capacitor results in a nominal 1ms before latch-off of
output after an OC event.
Reconfiguring the ISL6115AEVAL1Z board for a higher CR
level can be done by changing the R_SENSE and/or R_ISET
resistor values as the provided FET is rated for a much
higher current.
FIGURE 14. ISL6115AEVAL1Z HIGH SIDE SWITCH
APPLICATION and PHOTOGRAPH
8
FN6855.0
February 25, 2009