ISL6115A Datasheet, PDF (5/10 Pages) Intersil Corporation – 12V Power Distribution Controllers

ISL6115A
Description and Operation
The ISL6115A is targeted for +12V single power supply
distribution control for generic hot swap switching
applications.
This ICs features a highly accurate programmable current
regulation (CR) level with programmable time delay to
latch-off, and programmable soft-start turn-on ramp all set
with a minimum of external passive components. It also
includes severe OC protection that immediately shuts down
the MOSFET switch should a rapid load current transient such
as with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, it has an UV
indicator and an OC latch indicator. The functionality of the
PGOOD feature is enabled once the IC is biased, monitoring
and reporting any UV condition on the ISEN pin.
Upon initial power-up, the IC can either isolate the voltage
supply from the load by holding the external N-Channel
MOSFET switch off or apply the supply rail voltage directly to
the load for true hot swap capability. The PWRON pin must
be pulled low for the device to isolate the power supply from
the load by holding the external N-Channel MOSFET off.
With the PWRON pin held high or floating the IC will be in
true hot swap mode. In both cases the IC turns on in a
soft-start mode protecting the supply rail from sudden inrush
current.
At turn-on, the external gate capacitor of the N-Channel
MOSFET is charged with a 11µA current source resulting in
a programmable ramp (soft-start turn-on). The internal
ISL6115A charge pump supplies the gate drive for the 12V
supply switch driving that gate to ~V_DD +6.5V. Load current
passes through the external current sense resistor. When the
voltage across the sense resistor exceeds the user
programmed CR voltage threshold value, (see Table 1 for
R_ISET programming resistor value and resulting nominal
current regulation threshold voltage, V_CR) the controller
enters its current regulation mode. At this time, the time-out
capacitor, on CTIM pin is charged with a 20µA current source
and the controller enters the current limit time to latch-off
period. The length of the current limit time to latch-off duration
is set by the value of a single external capacitor (see Table 2)
for C_TIM capacitor value and resulting nominal current limited
time-out to latch-off duration placed from the CTIM pin (pin 6)
to ground. The programmed current level is held until either
the OC event passes or the time-out period expires. If the
former is the case then the N-Channel MOSFET is fully
enhanced and the C_TIM capacitor is discharged. Once C_TIM
charges to ~1.8V signaling that the time-out period has
expired, an internal latch is set whereby the FET gate is
quickly pulled to 0V turning off the N-Channel MOSFET
switch, isolating the faulty load.
TABLE 1. R_ISET PROGRAMMING RESISTOR VALUE
R_ISET RESISTOR
10kΩ
NOMINAL CR VTH
200mV
4.99kΩ
100mV
2.5kΩ
50mV
1.25kΩ
25mV
NOTE: Nominal Vth = R_ISET x 20µA.
TABLE 2. C_TIM CAPACITOR VALUE
C_TIM CAPACITOR NOMINAL CURRENT LIMITED PERIOD
0.022µF
2ms
0.047µF
4.4ms
0.1µF
9.3ms
NOTE: Nominal time-out period = C_TIM x 93kΩ.
This IC responds to a severe overcurrent load (defined as a
voltage across the sense resistor >150mV over the OC Vth set
point) by immediately driving the N-Channel MOSFET gate to
0V in about 10µs. The gate voltage is then slowly ramped up
turning on the N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
Upon a UV condition, the PGOOD signal will pull low when
connected through a resistor to the logic or VDD supply. This
pin is a UV fault indicator. For an OC latch-off indication,
monitor CTIM, pin 6. This pin will rise rapidly from 1.8V to
VDD once the time-out period expires.
See Figures 2 through 13 for graphs and waveforms related
to text.
The IC is reset after an OC latch-off condition by a low level
on the PWRON pin and is turned on by the PWRON pin
being driven high.
Application Considerations
Design applications where the CR Vth is set extremely low
(25mV or less), there is a two-fold risk to consider.
• There is the susceptibility to noise influencing the absolute
CR Vth value. This can be addressed with a 100pF
capacitor across the R_SET resistor.
• Due to common mode limitations of the overcurrent
comparator, the voltage on the ISET pin must be 20mV
above the IC ground either initially (from I_SET*R_SET) or
before C_TIM reaches time-out (from gate charge-up). If
this does not happen, the IC may incorrectly report
overcurrent fault at start-up when there is no fault. Circuits
with high load capacitance and initially low load current
are susceptible to this type of unexpected behavior.
Do not signal nor pull-up the PWRON input to > 5V.
Exceeding 6V on this pin will cause the internal charge pump
to malfunction.
During the soft-start and the time-out delay duration with the
IC in its current limit mode, the V_GS of the external N-Channel
MOSFET is reduced driving the MOSFET switch into a (linear
5
FN6855.0
February 25, 2009