ISL6115A Datasheet, PDF (3/10 Pages) Intersil Corporation – 12V Power Distribution Controllers

ISL6115A
Pin Descriptions
PIN # SYMBOL
FUNCTION
DESCRIPTION
1
ISET Current Set
Connect to the low side of the current sense resistor through the current limiting set resistor. This pin
functions as the current limit programming pin.
2
ISEN Current Sense
Connect to the more positive end of sense resistor to measure the voltage drop across this resistor.
3
GATE External FET Gate Drive Connect to the gate of the external N-Channel MOSFET. A capacitor from this node to ground sets
Pin
the turn-on ramp. At turn-on this capacitor will be charged to V_DD +6.5V by an 14µA current source.
4
VSS Chip Return
5
VDD Chip Supply
12V chip supply. This can be either connected directly to the +12V rail supplying the switched load
voltage or to a dedicated V_SS +12V supply.
6
CTIM Current Limit Timing
Connect a capacitor from this pin to ground. This capacitor determines the time delay between an
Capacitor
overcurrent event and chip output shutdown (current limit time-out). The duration of current limit
time-out is equal to 93kΩ x C_TIM.
7 PGOOD Power Good Indicator Indicates that the voltage on the ISEN pin is satisfactory. PGOOD is driven by an open drain
N-Channel MOSFET and is pulled low when the output voltage (VISEN) is less than the UV level for
the particular IC.
8 PWRON Power-ON
PWRON is used to control and reset the chip. The chip is enabled when PWRON pin is driven high
to a maximum of 5V or is left open. Do not drive this input >5V. After a current limit time-out, the chip
is reset by a low level signal applied to this pin. This input has 20µA pull-up capability.
3
FN6855.0
February 25, 2009