ISL54100A Datasheet, PDF (8/21 Pages) Intersil Corporation – TMDS Regenerators with Multiplexers

ISL54100A, ISL54101A, ISL54102A
Pin Descriptions
SYMBOL
DESCRIPTION
RX0-_A, RX0+_A, RX1-_A, RX1+_A, TMDS Inputs. Incoming TMDS data signals for Channel A.
RX2-_A, RX2+_A
RX0-_B, RX0+_B, RX1-_B, RX1+_B, TMDS Inputs. Incoming TMDS data signals for Channel B (ISL54100A and ISL54102A only).
RX2-_B, RX2+_B
RX0-_C, RX0+_C, RX1-_C, RX1+_C, TMDS Inputs. Incoming TMDS data signals for Channel C (ISL54100A only).
RX2-_C, RX2+_C
RX0-_D, RX0+_D, RX1-_D, RX1+_D, TMDS Inputs. Incoming TMDS data signals for Channel D (ISL54100A only).
RX2-_D, RX2+_D
RXC-_A, RXC+_A, RXC-_B, RXC+_B, TMDS Inputs. Incoming TMDS clock signals for Channels A, B, C and D (ISL54100A), Channels A and
RXC-_C, RXC+_C, RXC-_D, RXC+_D B (ISL54102A), or Channel A (ISL54101A).
TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TMDS Outputs. TMDS output data for selected channel.
TXC-, TXC+
TMDS Outputs. TMDS output clock for selected channel.
SCL
SDA
ADDR[6:0]
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
Note: Internal 65kΩ pull-up to V_D.
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
Note: Internal 65kΩ pull-up to V_D.
Digital inputs, 5V tolerant. 7-Bit address for serial interface.
Note: Internal 60kΩ pull-down to GND.
CH_SEL_0, CH_SEL_1
Digital inputs, 3.3V. Channel select inputs for stand-alone operation. Pull to ground with a 47k resistor if
unused.
AUTO_CH_SEL
Digital Input. Pull high to have the mux automatically select the highest channel (A is highest, D is lowest)
with an active TMDS clock. Low is manual channel select.
CHA_Active, CHB_Active,
CHC_Active, CHD_Active
Digital Outputs, 3.3V. Output goes high when there is an active TMDS clock on that channel's input. Used
for activity detect in a stand-alone configuration.
CHC_Active and CHD_Active are NC (do Not Connect) for the ISL54102A.
CHB_Active, CHC_Active and CHD_Active are NC (do Not Connect) for the ISL54101A.
RES_BIAS
RES_TERM
PD
RESET
TEST
V_D
V_D_ESD
GND
Tie to GND through a 3.16k external resistor. Sets up internal bias currents.
Tie to VD through a 1.0k 1% external resistor. During calibration, the termination resistor closest in value
to RES_TERM/20 (= 50Ω) is selected.
Digital Input, 3.3V. PD = Power-down. Pull high to put the ISL5410xA in a minimum power consumption
mode.
Note: To ensure proper operation, this pin must be held low during power-up. It may be taken high 100ms
after the power supplies have settled to 3.3V ±10%.
When exiting Power-down, a termination resistor Recalibration cycle must be run to re-trim the
termination resistors (see register 0x03[7]).
Note: Internal 60kΩ pull-down to GND.
Digital Input, 3.3V. Pull high then low to reset the mux. Tie to GND in final application.
Note: Internal 60k pull-down to GND.
Digital Input. Used for production testing only. Tie to GND in final application. This pin has an internal
pulldown to GND, so it is also acceptable to leave this pin floating.
Power supply. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.
Power supply for ESD protection diodes. Connect one of these pins (pin 74 or 95) to the 3.3V V_D supply
rail with a low V_F (0.4V or lower) Schottky diode, with the cathode connected to V_D_ESD and the anode
connected to V_D. Bypass each pin to GND with 0.1µF.
Ground return for V_D.
8
FN6725.0
June 17, 2008