ISL35411 Datasheet, PDF (8/11 Pages) Intersil Corporation – Quad Driver

ISL35411
Application Information
Typical application schematic for ISL35411 is shown in Figure 5.
De-Emphasis
Control
for Channels
1 and 2
1.2V ₁
IN1[P]
2
IN1[N]
3
TDSBL1 ₄
1.2V ₅
IN2[P]
6
IN2[N]
7
TDSBL2 ₈
1.2V ₉
IN3[P] ₁₀
IN3[N] ₁₁
TDSBL3
12
1.2V
13
IN4[P]
14
IN4[N]
15
ISL35411
A
OUT1[P]
38
OUT1[N]
37
1.2V
36
35 ^1.2V
OUT2[P]
34
OUT2[N]
33
1.2V
32
31 ^1.2V
OUT3[P]
30
OUT3[N]
29
28 ^1.2V
27 ^1.2V
26 ^OUT4[P]
25 ^OUT4[N]
24 ^1.2V
1.2V
De-Emphasis
Control
for Channels
3 and 4
Bypass circuit for each V_DD pin
(*100pF capacitor should be positioned closest to the pin)
A) DC Blocking Capacitors = X7R or COG
0.1µF (>6GHz bandwidth)
NOTES:
13. See “Adjustable De-emphasis” on page 7 for information on how to connect the DE pins.
14. See “Line Silence/Quiescent Mode” on page 7 for details on DT pin operation.
FIGURE 5. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL35411
8
FN6971.1
March 25, 2010