ISL35411 Datasheet, PDF (7/11 Pages) Intersil Corporation – Quad Driver

ISL35411
IN[P]
IN[N]
Limiting
Amplifier
Adjustable
De-Emphasis
Pre-
Driver
TDSBL
Output
Driver
OUT[P]
OUT[N]
DT
Signal
Detector
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE ISL35411
Adjustable De-emphasis
ISL35411 features a settable de-emphasis driver for
custom signal restoration.
The voltages at the DE pins are used to determine the
de-emphasis levels of each 2-channel group – from 0dB
to 4dB in 0.5dB increments. For each two of the four
channels the [A] and [B] control pins DE[k] are
associated with a non binary word. [A] and [B] can take
one of three different values: ‘LOW’, ‘MIDDLE’, or ‘HIGH’.
This is achieved by leaving the DE pins floating or
connecting them either to VDD or GND through 0Ω
resistors. Table 1 defines the mapping from the 2-bit DE
word to the 7 possible de-emphasis levels.
TABLE 1. MAPPING BETWEEN DE-EMPHASIS LEVEL
AND DE-PIN CONNECTIVITY
DE PIN
CONNECTION
DE[A] DE[B]
NOMINAL
DE-EMPHASIS LEVEL;
10.3125Gbps TO DE-EMPHASIS
11.1Gbps (dB)
SETTING
Open Open
0
0
Open GND
0.6
1
Open VDD
1.1
2
GND Open
1.6
3
GND
GND
2.3
4
GND
VDD
3
5
VDD Open
4
6
Line Silence/Quiescent Mode
The ISL35411 is capable of maintaining periods of line
silence by monitoring its input pins for loss of signal
(LOS) conditions and subsequently muting the output
drivers when such a condition is detected. A reference
voltage applied to the detection threshold DT[k] pins is
used to set the LOS threshold of the internal signal
detection circuitry. For most applications, it is
recommended to leave the DT pin floating at its default
internal bias. If the sensitivity of the detection threshold
needs to be adjusted, the DT voltage can be adjusted
with an external pull-up resistor. The resistor values
should be validated on an application-specific basis.
Connect the DT pin to ground in order to disable this
feature and prevent the outputs from muting during line
silence.
PCB Layout Considerations
Because of the high speed of the ISL35411 signals,
careful PCB layout is critical to maximize performance.
The following guidelines should be adhered to as closely
as possible:
• All high speed differential pair traces should have a
characteristic impedance of 50Ω with respect to
ground plane and 100Ω with respect to each other.
• Avoid using vias for high speed traces as this will
create discontinuity in the traces’ characteristic
impedance.
• Input and output traces need to have DC blocking
capacitors (100nF). Capacitors should be placed as
close to the chip as possible.
• For each differential pair, the positive trace and the
negative trace need to be of the same length in order
to avoid intra-pair skew. A Serpentine technique may
be used to match trace lengths.
• Maintain a constant solid ground plane underneath
the high-speed differential traces.
• Each VDD pin should be connected to 1.2V and also
bypassed to ground through a 10nF and a 100pF
capacitor in parallel. Minimize the trace length and
avoid vias between the VDD pin and the bypass
capacitors in order to maximize the power supply
noise rejection.
• If 4 channels of the device are set to the same boost,
then the quantity of CP resistors can be reduced by
tying both CP pins together.
7
FN6971.1
March 25, 2010