ISL32172E Datasheet, PDF (8/20 Pages) Intersil Corporation – QUAD, ±16.5kV ESD Protected, 3.0V to 5.5V, Low Power, RS-422 Transmitters

ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E
Electrical Specifications Test Conditions: V_CC = 3.0V to 3.6V and 4.5V to 5.5V; V_L = V_CC (ISL32179E only); Typicals are at V_CC = 3.3V
or V_CC = 5V, T_A = +25°C; Unless Otherwise Specified.(Notes 6, 10) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 9) TYP (Note 9) UNITS
Driver Disable from Output High
t_HZ SW = GND (see Figure 3)
Full
-
Driver Disable from Output Low
t_LZ
SW = V_CC (see Figure 3)
Full
-
Driver Enable from SHDN to High
t_SDH ISL32179E Only, SW = GND (see Figure 3,
Full
-
Note 13)
-
20
ns
-
20
ns
-
750
ns
Driver Enable from SHDN to Low
t_SDL ISL32179E Only, SW = V_CC (see Figure 3,
Full
-
Note 13)
-
750
ns
DRIVER SWITCHING CHARACTERISTICS (ISL32172E, ISL32174E, ISL32179E, 32Mbps)
Maximum Data Rate
f_MAX V_OD = ±1.5V, C_D = 100pF (see Figure 4)
Full
Driver Single-Ended Output Delay t_PLH, t_PHL R_DIFF = 100Ω, C_D = 50pF (see Figure 2)
Full
Driver Single-Ended Output Skew
t_SSK R_DIFF = 100Ω, C_D = 50pF (see Figure 2)
Full
Ch-to-Ch Output Delay Skew
t_SKCC (Figure 2, Note 11)
Full
Part-to-Part Output Delay Skew
t_SKPP (Figure 2, Note 8)
Full
Driver Differential Output Skew
t_DSK R_DIFF = 100Ω, C_D = 50pF (see Figure 2)
Full
Driver Differential Rise or Fall Time t_R, t_F R_DIFF = 100Ω, C_D = 50pF (see Figure 2)
Full
Driver Enable to Output High
t_ZH SW = GND (see Figure 3, Note 12)
Full
Driver Enable to Output Low
t_ZL
SW = V_CC (see Figure 3, Note 12)
Full
Driver Disable from Output High
t_HZ SW = GND (see Figure 3)
Full
Driver Disable from Output Low
t_LZ
SW = V_CC (see Figure 3)
Full
Driver Enable from SHDN to High
t_SDH ISL32179E Only, SW = GND (see Figure 3,
Full
Note 13)
32
50
-
Mbps
3
8
15
ns
-
1
3.5
ns
-
3
5.5
ns
-
-
8
ns
-
0.5
2
ns
-
7
12
ns
-
-
20
ns
-
-
20
ns
-
-
20
ns
-
-
20
ns
-
-
750
ns
Driver Enable from SHDN to Low
t_SDL ISL32179E Only, SW = V_CC (see Figure 3,
Full
-
Note 13)
-
750
ns
NOTES:
6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
7. Applies to peak current. See “Typical Performance Curves” beginning on page 12 for more information.
8. t_SKPP is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (V_CC,
temperature, etc.).
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. EN = 0 indicates that the output(s) under test are disabled via the appropriate logic pin settings. EN = 1 indicates that the logic pins are set to
enable the output(s) under test.
11. Channel-to-channel skew is the magnitude of the worst case delta between any two propagation delays of any two outputs on the same IC, at
the same test conditions.
12. For ISL32179E, keep SHDNEN low to avoid entering SHDN.
13. Keep SHDNEN high to enter SHDN when all transmitters are disabled (ISL32179E only).
14. Logic Pins are the DIs, the enable variants, and SHDNEN.
15. Only one of the SPX pins low, plus EN1-EN4 low with EN and EN high, or EN low and EN high with EN1-EN4 high.
16. Temperature range is -20°C to +40°C.
8
FN6824.0
December 16, 2008