ISL24006_06 Datasheet, PDF (8/10 Pages) Intersil Corporation – 14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator with Integrated 4-Channel Static Gamma Drivers

ISL24006
Data Byte
Data Bytes are the input code data to the 8-bit DACs. Most
significant bits are clocked in first. These data bytes
determine the output voltages of the ISL24006.
TABLE 4.
b₇
b₆
b₅
b₄
b₃
b₂
b₁
b₀
1
0
1
1
1
0
1
0
2⁷ × (1) + 2⁶ × (0) + 2⁵ × (1) + 2⁴ × (1) + 2³ × (1) + 2² × (0) + 2¹ × (1) + 2⁰ × (0)
Ideal Transfer Function Example
Given a typical voltage applied to V_{REFU_H} and V_{REFU_L}:
V_{REF U_H} = 14V
V_{REF U_L} = 8.5V
V_{REF L_H} = 6.5V
V_{REF L_L} = 1V
R = ¹----⁴----^V-----–-----⁸---^.--⁵---^V--- = 21.5mV
256
R = ⁶----^.--⁵---^V------–----¹----^V--- = 21.5mV
256
BINARY INPUT
00000000
00000001
00000011
00000111
00001111
00011111
00111111
01111111
11111111
TABLE 5.
DECIMAL VOUT1 (V)
0
8.5
1
8.521484
3
8.564453
7
8.650391
15
8.822266
31
9.166016
63
9.853516
127
11.22852
255
13.97852
VOUT14 (V)
1
1.021484
1.064453
1.150391
1.322266
1.666016
2.353516
3.728516
6.478516
Clock Oscillator
The ISL24006 require an internal clock or external clock to
refresh its outputs. The outputs are refreshed at the falling
OSC clock edges. The output refreshed switches open at
the rising edges of the OSC clock. The driving load shouldn't
be changed at the rising edges of the OSC clock. Otherwise,
it will generate a voltage error at the outputs. This clock may
be input or output via the clock pin labelled OSC. The
internal clock is provided by an internal oscillator running at
approximately 21kHz and can be output to the OSC pin. In a
two-chip system, if the driving loads are stable, one chip may
be programmed to use the internal oscillator; then the OSC
pin will output the clock from the internal oscillator. The
second chip may have the OSC pin connected to this clock
source.
For transient load application, the external clock mode
should be used to ensure all functions are synchronized
together. The positive edge of the external clock to the OSC
pin should be timed to avoid the transient load effect.
The Application Drawing shows the LCD H rate signal used,
here the positive clock edge is timed to avoid the transient
load of the column driver circuits. After power on, the chip
will default with the internal oscillator mode. At this time, the
OSC pin will be in a high impedance condition to prevent
contention.
Channel Outputs
Each of the channel outputs has a rail-to-rail buffer. This
enables all channels to have the capability to drive to within
50mV of the power rails (see Electrical Characteristics for
details).
When driving large capacitive loads, a series resistor should
be placed in series with the output. (Usually between 5Ω and
50Ω).
Each of the channels is updated on a continuous cycle. The
time for the new data to appear at a specific output will
depend on the exact timing relationship of the incoming data
to this cycle.
Power-On Sequencing
At power-on, make sure that A_VDD ≥ D_VDD - 0.5V to prevent
the ESD diode between A_VDD and D_VDD from driving too
much current. If D_VDD comes on first, leave A_VDD floating.
Do not ground A_VDD.
Power Dissipation
With the 30mA maximum continues output drive capability
for each channel, it is possible to exceed the 125°C absolute
maximum junction temperature. Therefore, it is important to
calculate the maximum junction temperature for the
application to determine if load conditions need to be
modified for the part to remain in the safe operation.
8
FN6110.1
March 9, 2006