ISL24006_06 Datasheet, PDF (2/10 Pages) Intersil Corporation – 14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator with Integrated 4-Channel Static Gamma Drivers

ISL24006
Absolute Maximum Ratings (T_A = 25°C)
Supply Voltage between A_VDD and GND . . . . . . . . . . . . . . . . .+18V
Supply Voltage between D_VDD and GND lesser of V_S or +7V (max)
Maximum Continuous Output Current
[V_{REFU_H}, V_{REFU_L}, V_{REFL_H}, V_{REFL_L]} . . . . . . . . . . . . . 60mA
[OUT1 to OUT14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Total Sourcing/Sink [Upper/Lower] . . . . . . . . . . . . . . . . . . 180mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. The device outputs cannot withstand short-
circuit condition for extended periods of time. To avoid damage, do not exceed absolute maximum rating of 20mA/channel.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T_J = T_C = T_A
Electrical Specifications A_VDD = 15V, D_VDD = 5V, V_{REFU_H} = 14V, V_{REFU_L} = 8.5V, V_{REFL_H} = 6.5V, V_{REFL_L} = 1V, R_L = 1kΩ and
C_L = 10pF to 1/2 A_VDD, T_A = 25°C, unless otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
SUPPLY
I_AVDD
I_DVDD
ANALOG
Supply Current
Digital Supply Current
No load
30
38
mA
2.75
4
mA
V_OH
V_OL
V_OH
V_OL
PSRR
V_AC
I_B
REG
BG
OUT1 to OUT7
OUT1 to OUT7
OUT8 to OUT14
OUT8 to OUT14
Power Supply Rejection Ratio
Accuracy
Input Bias Current,
V_{REF(U_H, U_L, L_H, L_L)}
Load Regulation
Band Gap
V_{REFU_H} = 14V, A_VDD = 15V
V_{REFU_L} = 8.5V, A_VDD = 15V
V_{REFL_H} = 6.5V, A_VDD = 15V
V_{REFL_L} = 1.0V, A_VDD = 15V
A_VDD is moved from 14V to 16V
V_REF = 1/2 A_VDD
I_OUT = 5mA step
13.94 13.98 14.02
V
8.47 8.51 8.55
V
6.44 6.48 6.52
V
0.96 1.00 1.04
V
42
50
dB
-50
0
+50
mV
2
50
nA
0.5
mV/mA
1.1
1.3
1.4
V
SR
Slew Rate
8
15
V/µs
t_S
DIGITAL
Settling Time
±1/2 LSB
1
µs
V_IH
Logic 1 Input Voltage
D_VDD-
V
20%
V_IL
F_CLK
R_SDIN
t_S
t_H
Logic 0 Input Voltage
Clock Frequency
S_DIN Input Resistance
Setup Time
Hold Time
SCL, SDA, STD_REG
20%*
V
D_VDD
400
kHz
1
GΩ
40
ns
40
ns
2
FN6110.1
March 9, 2006