ISL24006_06 Datasheet, PDF (6/10 Pages) Intersil Corporation – 14-Channel Programmable Switchable I2C TFT-LCD Reference Voltage Generator with Integrated 4-Channel Static Gamma Drivers

ISL24006
General Description
The ISL24006 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear. However, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the ISL24006,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the 14 reference voltage outputs can be set with a 8-
bit resolution. The first half of the output buffers, OUT1 to
OUT7 can be operated from V_{REFU_L} to V_{REFU_H}. The
second half OUT8 to OUT14 can swing from V_{REFL_L} to
V_{REFL_H}.
It is also possible to use the ISL24006 for applications other
than LCDs where multiple voltage references are required
that can be set to 8-bit accuracy.
Digital Interface
The ISL24006 uses a simple two-wire I²C interface to
program all 14 outputs. The bus line SCLK is the clock signal
line and bus SDA is the bi-directional data information signal
line. The ISL24006 can support a clock rate up to 400kHz.
An external pull up typically 1kΩ resistor is required for each
bus line.
Start and Stop Condition
A Start condition is a high to low transition on the serial data
line (SDA) line while the serial clock line (SCLK) holds high.
The Stop condition is a low to high transition on the SDA line
while SCLK is high. The master device always generates
Start and Stop conditions. The bus is considered to be busy
after the Start condition and to be free at a certain time
interval after the Stop condition. The two bus lines must be
high when the buses are not in use. The I²C Timing Diagram
2 (Figure 2) shows the format.
Data Validity
The data on the SDA line must be stable (clearly defined as
HI or LO) during the HI period of the clock signal. SDA
transition can only change when the clock signal on the
SCLK line is LO.
gg
Start, Stop and Timing Details of I²C Interface
Start Condition
Data Clocked in
Stop Condition
SDA
DATA
SCL
CLOCK
tS tH
tS
tH
tR
tF
Byte Format
Every byte put along the SDA line must be eight bits long.
The number of bytes that can be transmitted between a Start
and Stop condition is unrestricted. Data is always transferred
with the most significant bit (MSB) first.
Acknowledge
Each byte is followed by an acknowledge bit.
When a master device is sending data (WRITE) the master
puts a resistive high level on the SDA line during the
acknowledge clock pulse. The peripheral that
acknowledges, which is the receiver, has to pull down the
SDA line during the acknowledge pulse.
When a master device is receiving data (READ) the slave
puts a resistive high level on the SDA line during the
acknowledge clock pulse. The master will acknowledge by
pulling down the SDA line during the acknowledge pulse.
Not Acknowledge
A Not Acknowledge (NA) is when the receiver does not pull
down the SDA line during the acknowledge pulse: SDA line
remains in the HI or in a high impedance state.
A Not Acknowledge is the master device's signal to the slave
device to release the SDA line so the master device can
generate a Stop signal on the same line. The NA indicates
that data just received is the last byte of the data transfer.
Standard Mode
When pin #6 (STD_REG) is pulled high, the part operates in
Standard Mode, which is more commonly used than the
Register Mode. In the Standard Mode, the user can program
all outputs in one data stream or transfer frame.
For the Standard Mode in a WRITE transfer, a master device
sends data to program all the output buffers of the ISL24006.
The input data byte (DATA 1) to the first channel (OUT1) is
the third byte following the control byte. The second channel
(OUT2) is programmed by the fourth byte (DATA 2), and so
on. Each byte is followed by an acknowledge bit.
FIGURE 4. I²C TIMING DIAGRAM 2
6
FN6110.1
March 9, 2006