ICL7662_06 Datasheet, PDF (8/10 Pages) Intersil Corporation – CMOS Voltage Converter

ICL7662
V+
10µF
+
C_{1 -}
1
8
2
7
ICL7662
3
6
4
5
-
10µF ₊
16A.
R_{O VOUT}
-
V_OUT = -V+
C₂
V+
+
16B.
FIGURE 16. SIMPLE NEGATIVE CONVERTER AND ITS
OUTPUT EQUIVALENT
Output Ripple
ESR also affects the ripple voltage seen at the output. The
total ripple is determined by 2V, A and B, as shown in Figure
16. Segment A is the voltage drop across the ESR of C₂ at
the instant it goes from being charged by C₁ (current flowing
into C₂) to being discharged through the load (current
flowing out of C₂). The magnitude of this current change is 2
x I_OUT, hence the total drop is 2 x I_OUT x ESRC₂V.
Segment B is the voltage change across C₂ during time t₂,
the half of the cycle when C₂ supplies current the load. The
drop at B is I_OUT x t₂/C₂V. The peak-to-peak ripple voltage
is the sum of these voltage drops:
V_RIPPLE
≅


--------------------¹---------------------
2 × f_PUMP × C₂
+
2
ESRC₂
×
I_O
U

T
Again, a low ESR capacitor will result in a higher
performance output.
Paralleling Devices
Any number of ICL7662 voltage converters may be
paralleled (Figure 18) to reduce output resistance. The
reservoir capacitor, C₂, serves all devices while each device
requires its own pump capacitor, C₁. The resultant output
resistance would be approximately:
R_OUT =
R_OUT (of ICL7662)
n (number of devices)
Cascading Devices
The ICL7662 may be cascaded as shown in Figure 19 to
produce larger negative multiplication of the initial supply
voltage. However, due to the finite efficiency of each device,
the practical limit is 10 devices for light loads. The output
voltage is defined by:
V_OUT = -n(V_IN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7662
R_OUT values.
t₂
t₁
0
V
- (V+)
B
A
FIGURE 17. OUTPUT RIPPLE
V+
1
8
2 _ICL7662 7
1
8
C₁
3
“1”
6
4
5
2 _ICL7662 7
R_L
C₁
3
“N”
6
4
5
-
+ ^C2
FIGURE 18. PARALLELING DEVICES
8