ICL7662_06 Datasheet, PDF (7/10 Pages) Intersil Corporation – CMOS Voltage Converter

ICL7662
8
S₁
V_IN
3
S₃
2
S₂
C₁
S₄
4
3
C₂
V_OUT = -V_IN
5
7
FIGURE 15. IDEALIZED NEGATIVE CONVERTER
Theoretical Power Efficiency
Considerations
In theory a voltage multiplier can approach 100% efficiency if
certain conditions are met:
1. The drive circuitry consumes minimal power.
2. The output switches have extremely low ON resistance
and virtually no offset.
3. The impedances of the pump and reservoir capacitors are
negligible at the pump frequency.
The ICL7662 approaches these conditions for negative
voltage multiplication if large values of C₁ and C₂ are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E = 1/2C₁ (V₁₂ - V₂₂)
where V₁ and V₂ are the voltages on C₁ during the pump
and transfer cycles. If the impedances of C₁ and C₂ are
relatively high at the pump frequency (refer to Figure 15)
compared to the value of R_L, there will be a substantial
difference in the voltages V₁ and V₂. Therefore it is not only
desirable to make C₂ as large as possible to eliminate output
voltage ripple, but also to employ a correspondingly large
value for C₁ in order to achieve maximum efficiency of
operation.
Do’s and Don’ts
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply volt-
ages greater than 10V.
3. When using polarized capacitors, the + terminal of C₁
must be connected to pin 2 of the ICL7662 and the + ter-
minal of C₂ must be connected to GROUND.
4. If the voltage supply driving the 7662 has a large source
impedance (25Ω - 30Ω), then a 2.2µF capacitor from pin
8 to ground may be required to limit rate of rise of input
voltage to less than 2V/µs.
5. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will occur
under these conditions.
A 1N914 or similar diode placed in parallel with C₂ will
prevent the device from latching up under these conditions.
(Anode pin 5, Cathode pin 3).
Typical Applications
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
16 shows typical connections to provide a negative supply
where a positive supply of +4.5V to 20.0V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltages below 10V.
The output characteristics of the circuit in Figure 16A can be
approximated by an ideal voltage source in series with a
resistance as shown in Figure 16B. The voltage source has
a value of -(V+). The output impedance (R_O) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 2), the switching frequency, the value of C₁ and C₂,
and the ESR (equivalent series resistance) of C₁ and C₂. A
good first order approximation for R_O is:
R_O ≅ 2(R_SW1 + R_SW3 + ESRC₁)
1
+ 2(R_SW2 + R_SW4 + ESRC₁) + _{fPUMP x C1} + ESRC₂
(f_PUMP =
f_OSC ,
2
R_SWX = MOSFET switch resistance)
Combining the four R_SWX terms as R_SW, we see that
1
R_O ≅ 2 x R_SW + _{fPUMP x C1} + 4 x ESRC₁ + ESRC₂Ω
R_SW, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance
graphs), typically 24Ω at +25^oC and 15V, and 53Ω at +25^oC
and 5V. Careful selection of C₁ and C₂ will reduce the
remaining terms, minimizing the output impedance. High
value capacitors will reduce the 1/(f_PUMP x C₁) component,
and low FSR capacitors will lower the ESR term. Increasing
the oscillator frequency will reduce the 1/(f_PUMP x C₁) term,
but may have the side effect of a net increase in output
impedance when C₁ > 10µF and there is no longer enough
time to fully charge the capacitors every cycle. In a typical
application where f_OSC = 10kHz and C = C₁ = C₂ = 10µF:
1
R_O ≅ 2 x 23 + _{(5 x 103 x 10 x 10-6)} + 4 ESRC₁ + ESRC₂
R_O ≅ 46 + 20 + 5 x ESR_CΩ
Since the ESRs of the capacitors are reflected in the output
impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(f_PUMP x C₁) term, rendering
an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs as
high as 10Ω.
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