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HC5526 Datasheet, PDF (8/18 Pages) Intersil Corporation – ITU CO/PABX SLIC with Low Power Standby
HC5526
ITIP TIP
RING
IRING
+
-
ITIP
IRING
LOOP CURRENT
CIRCUIT
IRSN
-
+
HC5526
SATURATION GUARD
CIRCUIT
A1
I1
-5V
A2
I2
-5V
FIGURE 13. DC LOOP CURRENT
-
+
R1-
+
VTX
RSN
RDC
-2.5V
RRX
RDC1
RDC2
CDC
RSG
RSG
-5V
For loop resistances that result in a tip to ring voltage less than
the saturation guard voltage the loop current is defined as:
IL
=
-------------2----.-5----V---------------
RDC1 + RDC2
×
1000
(EQ. 1)
where: IL = Constant loop current.
RDC1 and RDC2 = Loop current programming resistors.
Capacitor CDC between RDC1 and RDC2 removes the VF
signals from the battery feed control loop. The value of CDC
is determined by Equation 2:
CDC
=
T
×


R-----D--1--C-----1-
+
R-----D--1--C-----2-
(EQ. 2)
where T = 30ms.
The minimum CDC value is obtained if RDC1 = RDC2.
Figure 14 illustrates the relationship between the tip to ring
voltage and the loop resistance. For a 0Ω loop resistance both
tip and ring are at VBAT/2. As the loop resistance increases, so
does the voltage differential between tip and ring. When this
differential voltage becomes equal to the saturation guard
voltage, the operation of the SLIC’s loop feed changes from a
constant current feed to a resistive feed. The loop current in the
resistive feed region is no longer constant but varies as a
function of the loop resistance.
VBAT = -48V, IL = 23mA, RSG = 21.4kΩ
0
SATURATION
VTIP
GUARD VOLTAGE
-10
CONSTANT CURRENT
FEED REGION
-20
RESISTIVE FEED
REGION
-30
-40
-50
0
SATURATION
GUARD VOLTAGE
1.2K
LOOP RESISTANCE (Ω)
FIGURE 14. VTR vs RL
VRING
∞
Figure 15 shows the relationship between the saturation guard
voltage, the loop current and the loop resistance. Notice from
Figure 15 that for a loop resistance <1.2kΩ (RSG = 21.4kΩ) the
SLIC is operating in the constant current feed region and for
resistances >1.2kΩ the SLIC is operating in the resistive feed
region. Operation in the resistive feed region allows long loop
and off-hook transmission by keeping the tip and ring voltages
off the rails. Operation in this region is transparent to the
customer.
50
VBAT = -48V, RSG = 21.4kΩ
40
30
CONSTANT CURRENT
FEED REGION
SATURATION GUARD
VOLTAGE, VTR = 38V
20
VBAT = -24V, RSG = ∞
10 RESISTIVE FEED
REGION
0
0
10
20
30
LOOP CURRENT (mA)
SATURATION GUARD
VOLTAGE, VTR = 13V
RL 100kΩ
RL 100kΩ
4kΩ
1.5kΩ
2kΩ
700Ω
<1.2kΩ RRSG = 21.4kΩ
<400Ω RRSG = ∞ Ω
FIGURE 15. VTR vs IL and RL
The Saturation Guard circuit (Figure 13) monitors the tip to
ring voltage via the transconductance amplifier A1. A1
generates a current that is proportional to the tip to ring
voltage difference. I1 is internally set to sink all of A1’s
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no RSG resistor) A1
supplies more current than I1 can sink. When this happens
A2 amplifies its input current by a factor of 12 and the current
through R1 becomes the difference between I2 and the
output current from A2. As the current from A2 increases, the
voltage across R1 decreases and the output voltage on RDC
decreases. This results in a corresponding decrease in the
loop current. The RSG pin provides the ability to increase the
saturation guard reference voltage beyond 12.5V. Equation 3
64