HC5526 Datasheet, PDF (14/18 Pages) Intersil Corporation – ITU CO/PABX SLIC with Low Power Standby

HC5526
SLIC Operating States
E0
E1
C1
C2
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
TABLE 1. LOGIC TRUTH TABLE
SLIC OPERATING STATE
ACTIVE DETECTOR
Open Circuit
No Active Detector
Active
Ground Key Detector
Ringing
No Active Detector
Standby
Ground Key Detector
DET OUTPUT
Logic Level High
Ground Key Status
Logic Level High
Ground Key Status
0
1
0
0
Open Circuit
0
1
0
1
Active
0
1
1
0
Ringing
0
1
1
1
Standby
No Active Detector
Loop Current Detector
Ring Trip Detector
Loop Current Detector
Logic Level High
Loop Current Status
Ring Trip Status
Loop Current Status
1
0
0
0
Open Circuit
1
0
0
1
Active
1
0
1
0
Ringing
1
0
1
1
Standby
No Active Detector
Ground Key Detector
No Active Detector
Ground Key Detector
Logic Level High
1
1
0
0
Open Circuit
1
1
0
1
Active
1
1
1
0
Ringing
1
1
1
1
Standby
Power-Up Sequence
The HC5526 has no required power-up sequence. This is a
result of the Dielectrically Isolated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
Printed Circuit Board Layout
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
The analog and digital grounds should be tied together at
the device.
Notes
2. Overload Level (Two-Wire port). The overload level is specified
at the 2-wire port (V_TR0) with the signal source at the 4-wire
receive port (E_RX). I_DCMET = 30mA, increase the amplitude of
E_RX until 1% THD is measured at V_TRO. Reference Figure 1.
3. Longitudinal Impedance. The longitudinal impedance is com-
puted using the following equations, where TIP and RING volt-
ages are referenced to ground. L_ZT, L_ZR, V_T, V_R, A_R and A_T
are defined in Figure 2.
(TIP) L_ZT = V_T/A_T,
(RING) L_ZR = V_R/A_R,
where: E_L = 1V_RMS (0Hz to 100Hz).
70
No Active Detector
Loop Current Detector
Ring Trip Detector
Loop Current Detector
4. Longitudinal Current Limit (Off-Hook Active). Off - Hook (Ac-
tive, C₁ = 1, C₂ = 0) longitudinal current limit is determined by
increasing the amplitude of E_L (Figure 3A) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
5. Longitudinal Current Limit (On-Hook Standby). On - Hook
(Active, C₁ = 1, C₂ = 1) longitudinal current limit is determined
by increasing the amplitude of E_L (Figure 3B) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains high
(no false detection).
6. Longitudinal to Metallic Balance. The longitudinal to metallic
balance is computed using the following equation:
BLME = 20 • log (E_L/V_TR), where: E_L and V_TR are defined in
Figure 4.
7. Metallic to Longitudinal FCC Part 68, Para 68.310. The
metallic to longitudinal balance is defined in this spec.
8. Longitudinal to Four-Wire Balance. The longitudinal to 4-wire
balance is computed using the following equation:
BLFE = 20 • log (E_L/V_TX),: E_L and V_TX are defined in Figure 4.
9. Metallic to Longitudinal Balance. The metallic to longitudinal
balance is computed using the following equation:
BMLE = 20 • log (E_TR/V_L), E_RX = 0,
where: E_TR, V_L and E_RX are defined in Figure 5.
10. Four-Wire to Longitudinal Balance. The 4-wire to longitudinal
balance is computed using the following equation:
BFLE = 20 • log (E_RX/V_L), E_TR = source is removed,
where: E_RX, V_L and E_TR are defined in Figure 5.