FN6579 Datasheet, PDF (8/14 Pages) Intersil Corporation – Negative Signal Swing, Sub-ohm, Dual SPDT Single Supply Switch

ISL54059
Test Circuits and Waveforms (Continued)
*50Ω SOURCE
V+
C
SIGNAL
GENERATOR
NO OR NC
ANALYZER
R_L
IN 0V OR V+
COM
GND
r_ON = V₁/100mA
NO OR NC
V_NX
100mA
V₁
V+
C
0V OR V+
IN
COM
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
*50Ω SOURCE
SIGNAL
GENERATOR
V+
C
NO1 OR NC1
COM1
50Ω
IN_X
0V OR V+
ANALYZER
COM2
NC2 OR NO2
NC
GND
R_L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54059 is a bi-directional, dual single pole-double
throw (SPDT) analog switch that offers precise switching
from a single 1.8V to 6.5V supply with low ON-resistance
(0.83Ω) and high speed operation (t_ON = 55ns, t_OFF = 18ns).
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.8V), low power consumption (8nA), and a tiny 1.8x1.4mm
µTQFN package or a 3x3mm TDFN package. The low
ON-resistance and r_ON flatness provide very low insertion
loss and signal distortion for applications that require signal
switching with minimal interference by the switch.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. The ISL54059
8
Repeat test for all switches.
FIGURE 5. r_ON TEST CIRCUIT
V+
C
NO OR NC
IMPEDANCE
ANALYZER
IN 0V OR V+
COM
GND
COM is connected to NO or NC
during ON capacitance measurement.
FIGURE 7. CAPACITANCE TEST CIRCUIT
contains ESD protection diodes on each pin of the IC
(see Figure 8). These diodes connect to either a +Ring or
-Ring for ESD protection. To prevent forward biasing the
ESD diodes to the +Ring, V+ must be applied before any
input signals, and the input signal voltages must remain
between recommended operating range.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a logic pin or switch terminal goes
above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
FN6579.2
March 11, 2011