CD4512BMS Datasheet, PDF (8/8 Pages) Intersil Corporation – CMOS Dual 4-Bit Latch

CD4512BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T_A) = +25^oC
300
250
SUPPLY VOLTAGE (VDD) = 5V
200
150
100
10V
50
5V
0
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (“A” SELECT TO OUTPUT)
Chip Dimensions and Pad Layouts
0
75
70
10 20 30 40
50 60 70 78
60
50
40
72-80
(1.829-2.032)
30
20
10
0
4-10
(0.102-0.254)
75-83
(1.905-2.108)
Dimensions in parentheses are in milimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10^-3 inch.)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1187