CD4512BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS Dual 4-Bit Latch

CD4512BMS
December 1992
CMOS Dual 4-Bit Latch
Features
Pinout
• High-Voltage Types (20-Volt Rating)
• 3-State Outputs
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25^oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
CD4512BMS
TOP VIEW
D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
VSS 8
16 VDD
15 3-STATE DISABLE
14 SEL. OUTPUT
13 C
12 B
11 A
10 INHIBIT
9 D7
Functional Diagram
Applications
• Digital Multiplexing
• Number-sequence Generation
• Signal Gating
Description
CD4512BMS is an 8-channel data selector featuring a three-
state output that can interface directly with, and drive, data
lines of bus-oriented systems.
The CD4512BMS is supplied in these 16 lead outline
packages:
Braze Seal DIP
H4S
Frit Seal DIP
H1E
Ceramic Flatpack
H3X
3-STATE DISABLE
INHIBIT
10 15
D0-1
D1-2
CHANNELS
INPUTS
D2-3
D3-4
D4-5
SELECT
CONTROL
D5-6
D6-7
D7-9
A-11
B-12
C-13
CD4512BMS
14 SELECT
OUTPUT
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1180
File Number 3340