CD4512BMS Datasheet, PDF (6/8 Pages) Intersil Corporation – CMOS Dual 4-Bit Latch

CD4512BMS
Logic Diagram
C 13^*
B 12^*
A 11^*
D0 1 ^*
p
n
D1 2 ^*
p
n
D2 3 ^*
p
n
D3 4 ^*
p
n
3-STATE
INHIBIT DISABLE
10^*
15^*
p
n
p
n
p
n
D4 5 ^*
p
n
D5 6 ^*
p
n
D6 7 ^*
p
n
D7 9 ^*
p
n
p
n
p
n
p
n
* All inputs protected by CMOS protection network.
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
SELECT CONT.
ABC
000
100
010
110
001
101
011
111
XXX
XXX
1 = HIGH LEVEL
0 = LOW LEVEL
3-STATE
SELECT
INH
DISABLE OUTPUT
0
0
D0
0
0
D1
0
0
D2
0
0
D3
0
0
D4
0
0
D5
0
0
D6
0
0
D7
1
0
0
X
1
High Z
X = DON’T CARE
VDD
p
14
SELECT
OUTPUT
n
VSS
VDD
VSS
7-1185