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X9429_08 Datasheet, PDF (7/20 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer(XDCP™)
X9429
TABLE 1. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3 I2 I1 I0 R1 R0 X1 X0
OPERATION
Read Wiper Counter Register 1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register
Write Wiper Counter Register 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register
Read Data Register
Write Data Register
XFR Data Register to Wiper
Counter Register
1 0 1 1 1/0 1/0 0
1 1 0 0 1/0 1/0 0
1 1 0 1 1/0 1/0 0
0 Read the contents of the Data Register pointed to by R1 - R0
0 Write new value to the Data Register pointed to by R1 - R0
0 Transfer the contents of the Data Register pointed to by R1 - R0
to its Wiper Counter Register
XFR Wiper Counter
Register to Data Register
Increment/Decrement Wiper
Counter Register
1 1 1 0 1/0 1/0 0
00100 0 0
0 Transfer the contents of the Wiper Counter Register to the Data
Register pointed to by R1 - R0
0 Enable Increment/decrement of the Wiper Counter Register
Read Wiper Counter Register (read the current wiper
position of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected nonvolatile
register) and write Data Register (write a new value to the
selected Data Register). The sequence of operations is
shown in Figure 4.
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9429 has responded with an acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH, the
selected wiper will move one resistor segment towards the
VH/RH terminal. Similarly, for each SCL clock pulse while
SDA is LOW, the selected wiper will move one resistor
segment towards the VL/RL terminal. A detailed illustration of
the sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
NOTE: (1)1/0 = data is one or zero
SCL
SDA
S 0 1 0 1 A3 A2 0 A0 A I3 I2 I1 I0 R1 R0 0 0 A 0 0 D5 D4 D3 D2 D1 D0 A S
T
C
C
CT
A
K
K
KO
R
P
T
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S 0 1 0 1 A3 A2 0 A0 A I3 I2 I1 I0 R1 R0 0 0 A I I
T
C
CNN
A
K
KCC
R
12
T
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
ID
NE
CC
n1
DS
ET
CO
nP
7
FN8248.3
October 13, 2008