X9429_08 Datasheet, PDF (6/20 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer(XDCP™)

X9429
Four of the seven instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the Data
Registers. A transfer from a Data Register to a Wiper
Counter Register is essentially a write to a static RAM. The
response of the wiper to this action will be delayed t_WRL. A
transfer from the Wiper Counter Register (current wiper
position), to a Data Register is a write to non-volatile
memory and takes a minimum of t_WR to complete.
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9429; either between the host and one of the Data Registers
or directly between the host and the Wiper Counter Register.
These instructions are:
Flow 1. ACK Polling Sequence
NON-VOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS
ACK
NO
RETURNED?
YES
FURTHER
NO
OPERATION?
YES
ISSUE
INSTRUCTION
ISSUE STOP
ISSUE STOP
PROCEED
PROCEED
SCL
SDA
S 0 1 0 1 A3 A2 0 A0 A I3 I2 I1 I0 R1 R0 0 0 A S
T
C
CT
A
K
KO
R
P
T
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
6
FN8248.3
October 13, 2008