X9429_08 Datasheet, PDF (5/20 Pages) Intersil Corporation – Single Digitally Controlled Potentiometer(XDCP™)

X9429
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9429 will be
considered a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t_LOW). SDA state changes during SCL HIGH
are reserved for indicating start and stop conditions.
Start Condition
All commands to the X9429 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t_HIGH). The X9429 continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is
HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period, the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9429 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9429 will
respond with a final acknowledge.
Array Description
The X9429 is comprised of a resistor array. The array
contains 63 discrete resistive segments that are connected
in series. The physical ends of the array are equivalent to
the fixed terminals of a mechanical potentiometer (V_H/R_H
and V_L/R_L inputs).
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper (V_W/R_W)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The six bits of the WCR are
decoded to select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing. The most significant four
bits of the slave address are the device type identifier (refer
to Figure 1). For the X9429 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
0
1
0
1 A3 A2 0
A0
DEVICE ADDRESS
FIGURE 1. SLAVE ADDRESS
The next four bits of the slave address are the device address.
The physical device address is defined by the state of the A₀,
A₂, and A₃ inputs. The X9429 compares the serial data
stream with the address input state; a successful compare of
all three address bits is required for the X9429 to respond with
an acknowledge. The A₀, A₂, and A₃ inputs can be actively
driven by CMOS input signals or tied to V_CC or V_SS.
Acknowledge Polling
The disabling of the inputs, during the internal non-volatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the non-volatile write command,
the X9429 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the device slave address. If the X9429
is still busy with the write operation, no ACK will be returned.
If the X9429 has completed the write operation, an ACK will
be returned, and the master can then proceed with the next
operation.
Instruction Structure
The next byte sent to the X9429 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of four
associated registers. The format is shown in Figure 2.
REGISTER
SELECT
I3 I2 I1 I0 R1 R0 0
0
INSTRUCTIONS
FIGURE 2. INSTRUCTION BYTE FORMAT
The four high order bits define the instruction. The next two
bits (R₁ and R₀) select one of the four registers that is to be
acted upon when a register oriented instruction is issued.
Bits 0 and 1 are defined to be 0.
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FN8248.3
October 13, 2008