X9258 Datasheet, PDF (7/20 Pages) Xicor Inc. – Quad Digital Controlled Potentiometers (XDCP)

X9258
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
Data Output
from Transmitter
Data Output
from Receiver
START
Figure 8. Detailed Potentiometer Block Diagram Detailed Operation
9
Acknowledge
Serial Data Path
From Interface
Circuitry
Register 0
Register 2
If WCR = 00[H] then V_W/R_W = V_L/R_L
If WCR = FF[H] then V_W/R_W = V_H/R_H
Serial
BUS
Input
C
Register 1
o
u
8
8
Parallel
BUS
Input
n
t
e
r
Register 3
Wiper
Counter
D
Register
e
(WCR)
c
o
d
e
UP/DN
INC/DEC
Logic
UP/DN
Modified SCL
CLK
V_H/R_H
V_L/R_L
All DCP potentiometers share the serial interface and
share a common architecture. Each potentiometer has
a Wiper Counter Register and four Data Registers. A
detailed discussion of the register organization and
array operation follows.
Wiper Counter Register
The X9258 contains four Wiper Counter Registers,
one for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
7
V_W/R_W
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction. Finally, it is loaded with the contents of its
data register zero (R0) upon power-up.
FN8168.1
May 6, 2005