X9258 Datasheet, PDF (14/20 Pages) Xicor Inc. – Quad Digital Controlled Potentiometers (XDCP)

X9258
DCP TIMING
Symbol
t_WRPO
t_WRL
t_WRID
Parameter
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
Min. Max.
10
10
10
Unit
µs
µs
µs
Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling
edge of SCL.
TIMING DIAGRAMS 2-WIRE INTERFACE
START and STOP Timing
(START)
SCL
t_SU:STA
SDA
t_R
t_HD:STA
t_R
t_F
t_SU:STO
t_F
(STOP)
Input Timing
t_CYC
SCL
SDA
Output Timing
t_SU:DAT
t_HIGH
t_LOW
t_HD:DAT
t_BUF
SCL
SDA
t_AA
t_DH
14
FN8168.1
May 6, 2005