X9258 Datasheet, PDF (4/20 Pages) Xicor Inc. – Quad Digital Controlled Potentiometers (XDCP)

ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
No
Returned?
Yes
Further
No
Operation?
Yes
Issue
Instruction
Proceed
Issue STOP
Issue STOP
Proceed
X9258
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the Wiper Counter Register
and one of the data registers. A transfer from a Data
Register to a Wiper Counter Register is essentially a
write to a static RAM. The response of the wiper to this
action will be delayed t_WRL. A transfer from the Wiper
Counter Register (current wiper position), to a data
register is a write to nonvolatile memory and takes a
minimum of t_WR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all of the potentiometers
and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9258; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are: Read Wiper Counter Register (read the current
wiper position of the selected pot), Write Wiper
Counter Register (change current wiper position of the
selected pot), Read Data Register (read the contents
of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data
register). The sequence of operations is shown in
Figure 4.
Instruction Structure
The next byte sent to the X9258 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3 I2 I1 I0 R1 R0 P1 P0
Instructions
Wiper Counter
Register Select
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers
that is to be acted upon when a register oriented
instruction is issued. The last bits (P1, P0) select
which one of the four potentiometers is to be affected
by the instruction.
4
FN8168.1
May 6, 2005