ISL6719 Datasheet, PDF (7/9 Pages) Intersil Corporation – 100V Linear Bias Supply

ISL6719
AUXIN
AUXIN is the auxiliary input of the ISL6719, accepting bias
voltage whenever the input source voltage, VPWR, is above
its undervoltage lockout (UVLO) threshold. VSW selects
AUXIN as its source when it is capable supporting the load
on VSW. Otherwise VPWR is selected.
AUXIN can accept voltages up to 40V maximum. Voltages in
excess of 40V, including transients, will cause permanent
damage to the device. Care should be taken when
connecting external sources through very long traces or lead
wires. The lead inductance may cause unexpected
transients in excess of the device’s ratings. In such
circumstances it is recommended that a small resistor be
placed between AUXIN and the external source to dampen
the transient. A value of 10Ω to 100Ω is usually sufficient.
VSW
VSW is the switched output and may be turned on and off
using the ENABLE or ENABLE_N pins. VSW is adjustable
from 1.5V to 20V, but must always be at least 6.2V lower
than VPWR at rated load. Additionally, VSW must be at least
3.0V lower than AUXIN for it to function as the source for
VSW. As the differential voltage between AUXIN and VSW
drops below 3.0V, the input current will shift from AUXIN to
VPWR. The voltage headroom required is load dependent.
See Figures 1 and 2. VSW preferentially uses AUXIN as its
input source, but if AUXIN is unable to supply adequate
voltage, VPWR is selected as the alternate input source.
VSW is capable of delivering up to 100mA continuously,
depending on power dissipation and the thermal
environment in which the device is placed.
The output voltage is adjusted using the VSW_FB input.
VSW is set with a resistor divider from VSW to ground with
the central node connected to VSW_FB. Refer to Figure 5.
VSW
=
V_REF
R_{-----1-----+----}R_-----2-
R₂
–
I_BIASR₁
V
(EQ. 1)
Referring to Equation 1, V_REF is nominally 1.5V and I_BIAS
has a maximum value of 1.5µA. The error introduced by the
VSW_FB bias current can be minimized by making the
product of R₁ x I_BIAS small, relative to the magnitude of the
desired output voltage. For example, setting R₁ x I_BIAS
equal to 0.5% of VSW yields a value for R₁ equal to 3.33 x
VSW (kΩ).
VSW requires an external compensation capacitor to remain
stable across the output adjustment range, output
capacitance and loading. A value of 220pF between COMPA
and COMPB is recommended for all operating conditions
with a nominal load capacitance of 1.0µF (0.47µF to 1.5µF).
VSW requires a minimum load of 3mA.
VSW
R1
C2
1.0μF
1 _{VPWR GND} 9
ENABLE_N ⁸
2
ENABLE
AUXIN
7
3 _{VSW COMPB} 6
4
COMPA ₅
VSW_FB
R2
C3
220pF
FIGURE 5. VSW ADJUSTMENT AND COMPENSATION
TRACE 1: VSW
TRACE 2: I_VSW
FIGURE 6. VSW TRANSIENT RESPONSE, 10mA TO 100mA
STEP, VPWR = 18V, AUXIN = 15V, VSW = 12V
Figure 6 depicts the transient response of VSW during a
10mA to 100mA step load when AUXIN is set to 15V and
VPWR is set to 18V.
VPWR
VPWR provides the source voltage for the IC and load until
AUXIN is back biased. VSW is disabled and the IC operates
in a standby (low power consumption) mode when UVLO is
active.
7
FN6555.1
October 1, 2007