ISL6719 Datasheet, PDF (6/9 Pages) Intersil Corporation – 100V Linear Bias Supply

ISL6719
Typical Performance Curves (Continued)
1.002
1.001 VSW = 1.5V, AUXIN = 15V
VSW = 20V, AUXIN = 30V
VSW = 5V, AUXIN = 15V
1.000
0.999
VSW = 12V, AUXIN = 15V
0.998
VSW = 15V, AUXIN = 30V
0.997
-40 -25 -10 5 20 35 50 65 80 95 110
TEMPERATURE (°C)
FIGURE 3. VSW REGULATION vs TEMPERATURE @
VPWR = 100V, I_VSW = 3mA
1.0010
1.0005
1.0000
0.9995
VSW = 5V
VSW = 10V
VSW = 12V
0.9990
0
10 20 30 40 50 60 70 80 90 100
LOAD (mA)
FIGURE 4. VSW REGULATION vs LOAD @ VPWR = 18V,
AUXIN = 15V, +25°C
Pin Descriptions
VPWR
VPWR is the power connection for the IC. UVLO
enables/disables the output and places the device into a
standby mode even if AUXIN is externally biased.
To optimize noise immunity, bypass VPWR to GND with a
ceramic capacitor as close to the VPWR and GND pins as
possible.
AUXIN
This is the input for an external bias source typically
provided by an auxiliary transformer winding. This input is
not required and may be grounded or left open. Maximum
input bias is 40V.
ENABLE
The positive logic on/off control input. A logic high enables
VSW. Asserting this signal low turns off VSW. ENABLE and
ENABLE_N are logically ORed. Either signal can enable
VSW, but both must be false to disable VSW.
ENABLE_N
The negative logic on/off control input. A logic low enables
VSW. Asserting this signal high turns off VSW. ENABLE and
ENABLE_N are logically ORed. Either signal can enable
VSW, but both must be false to disable VSW.
GND
Signal and power ground connections for this device.
VSW
This is the switched regulated low voltage output supply that
is derived from VPWR or AUXIN. Its output is adjustable
from 1.5V to 20V using an appropriate divider from VSW to
VSW_FB. Protection circuitry prevents the output from
exceeding 25V in the event of a fault on VSW_FB (short high
or low). The minimum output current capability is 100mA.
VSW requires a minimum load of 3mA.
VSW_FB
The feedback pin for VSW. A divider from VSW to ground
sets feedback for VSW and determines the output voltage.
COMPA, COMPB
A compensating capacitor is placed between COMPA and
COMPB to stabilize the control loop. The values may vary
depending on the output load and capacitance applied
between VSW and GND, but for all applications having a
1.0µF load capacitor, a 220pF compensation capacitor is
recommended. The voltage at COMPA is nominally 0.7V.
The voltage at COMPB is nominally VSW +5.0V.
Functional Description
Features
The control circuitry used in Telecom/Datacom DC/DC
converters typically requires an operating bias voltage
significantly lower than the source voltage available to the
converter. Many applications use a discrete linear regulator
from the input source to create the bias supply. Often an
auxiliary winding from the power transformer is used to
supplement or replace the linear supply once the converter
is operating. The auxiliary winding bias voltage may require
regulation as well to minimize the voltage variation inherent
in slave windings. When implemented discretely, this
circuitry occupies significant PWB area, a considerable
problem in today’s high density converters.
The ISL6719 linear regulator simplifies the start-up and
operating bias circuitry needed in Telecom and Datacom
DC/DC converters by integrating these functions, and more,
in a small 3mm x 3mm DFN package.
6
FN6555.1
October 1, 2007