ISL6719 Datasheet, PDF (5/9 Pages) Intersil Corporation – 100V Linear Bias Supply

ISL6719
Electrical Specifications
PARAMETER
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application” on page 3. 17V < VPWR < 100V, C_VSW = 1μF, I_VSW = -3mA, VSW Enabled,
T_A = -40°C to +105°C (Note 4), Typical values are at T_A = +25°C. (Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Maximum VOUT, Faulted VSW_FB
VSW_FB = 0V, VPWR = 100V, AUXIN = 40V
22
25
V
Long Term Stability
T_A = +125°C, 1000 hours (Note 5),
0.3
%
VPWR = 48V, VSW = 10V, I_VSW = -10mA,
AUXIN = 15V
Operational Current (source)
VPWR = 48V, AUXIN = 17V, VSW = 15V
-100
mA
Current Limit
VPWR = 48V, AUXIN = 15V, VSW = 10V
-100
-230
-400
mA
VSW_FB Bias Current
VPWR = 100V, AUXIN = 40V, VSW = 10V,
-0.5
VSW_FB = 1.5V
1.5
µA
COMPA, COMPB Recommended
Capacitance
Note 5
170
220
270
pF
COMPA Voltage
0.7
V
COMPB Voltage
VSW + 5.0
V
ENABLE, ENABLE_N
High Level Input Voltage (VIH)
VPWR = 48V, AUXIN = 0V
2.5
3.0
3.6
V
Low Level Input Voltage (VIL)
VPWR = 48V, AUXIN = 0V
1.6
2.0
2.5
V
Hysteresis
VPWR = 48V, AUXIN = 0V
0.7
1.0
1.3
V
Pull-Up Resistance
Turn-On Delay
Turn-Off Delay
THERMAL PROTECTION
V_ENABLE =V_{N_ENABL} =0V
-
100
-
kΩ
T_VSW,10% - T_ENABLE, T_VSW,10% - T_{ENABLE_N,}
25
µs
I_VSW = -3mA
T_VSW,10% - T_ENABLE, T_VSW,10% - T_{ENABLE_N,}
40
µs
I_VSW = -50mA
Thermal Shutdown
150
°C
Thermal Shutdown Clear
95
°C
Hysteresis
55
°C
NOTE:
4. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.
5. Limits established by characterization and are not production tested.
Typical Performance Curves
5.5
2.5
5.0
4.5
2.0
4.0
1.5
3.5
3.0
0
20
40
60
80
100
VSW CURRENT (mA)
FIGURE 1. VPWR - VSW vs I_VSW @ AUXIN = 0V, +25°C
1.0 ₀
20
40
60
80
100
VSW CURRENT (mA)
FIGURE 2. AUXIN - VSW vs I_VSW @ VPWR = 17V, +25°C
5
FN6555.1
October 1, 2007