ISL6537A Datasheet, PDF (7/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

ISL6537A
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
LGATE (Pin 28)
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
FB (Pin 15) and COMP (Pin 16)
The V_DDQ switching regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. The V_DDQ output voltage is set by an external
resistor divider connected to FB. With a properly selected
divider, V_DDQ can be set to any voltage between the power
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for under and overvoltage
events.
PHASE (Pin 24)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
OCSET (Pin 22)
Connect a resistor (R_OCSET) from this pin to the drain of the
upper MOSFET. R_OCSET, an internal 20μA current source
(I_OCSET), and the upper MOSFET on-resistance (r_DS(ON))
set the converter overcurrent (OC) trip point according to the
following equation:
I_PEAK
=
I--_{O-----C----S----E----T----x---R-----O----C----S----E----T--}
r_DS(ON)
(EQ. 1)
An overcurrent trip cycles the soft-start function.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated V_DDQ output. During S0/S1 states, the VDDQ
pins serve as inputs to the V_TT regulator and to the V_TT
Reference precision divider.
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connected externally
together. During S0/S1 states, the DDR_VTT pins serve as
the outputs of the V_TT linear regulator. During S3 state, the
V_TT regulator is disabled.
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the V_TT linear
regulator. Connect this pin to the V_TT output at the physical
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of V_TT and also acts as the
reference voltage for the V_TT linear regulator. It is
recommended that a minimum capacitance of 0.1μF is
connected between V_DDQ and VREF_OUT and also
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, C_SS, connected between VREF_IN and ground
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (R_U||R_L), sets the
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
The minimum value for C_SS can be found through the
following equation:
C_SS > ^C---₁--^V-₀---^T--_â‹--^T-₂--^O-_A----^U--_â‹--^T-_R----^â‹-_U--^V---_|-^D_|---_R-^D---_L-^Q---
(EQ. 2)
The calculated capacitance, C_SS, will charge the output
capacitor bank on the V_TT rail in a controlled manner without
reaching the current limit of the V_TT LDO.
BOOT (Pin 25)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
PWM4 (Pin 19)
This pin provides the PWM output for the GMCH core
switching regulator. Connect this pin to the PWM input of an
Intersil MOSFET driver.
FB4 (Pin 19) and COMP4 (Pin 17)
The GMCH core switching regulator employs a single
voltage control loop. FB4 is the negative input to the voltage
loop error amplifier. The GMCH core output voltage is set by
an external resistor divider connected to FB4. With a
properly selected divider, V_GMCH can be set to any voltage
between the power rail (reduced by converter losses) and
the 0.8V reference. Loop compensation is achieved by
connecting an AC network across COMP4 and FB4.
The FB4 pin is also monitored for undervoltage events.
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FN9143.5