ISL6537A Datasheet, PDF(15/16 Page) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

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ISL6537A Datasheet, PDF (15/16 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

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ISL6537A

For a through hole design, several electrolytic capacitors

may be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These

capacitors must be capable of handling the surge-current at

power-up. Some capacitor series available from reputable

manufacturers are surge current tested.

MOSFET Selection - PWM Buck Converter

The ISL6537A requires 2 N-Channel power MOSFETs for

switching power and a third MOSFET to block backfeed from

VDDQ to the Input in S3 Mode. These should be selected

based upon rDS(ON), gate supply requirements, and thermal

management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor. The switching losses seen when

sourcing current will be different from the switching losses

seen when sinking current. When sourcing current, the

upper MOSFET realizes most of the switching losses. The

lower switch realizes most of the switching losses when the

converter is sinking current (see the equations below).

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the upper and lower MOSFETâs body diode. The

gate-charge losses are dissipated in part by the ISL6537A

and do not significantly heat the MOSFETs. However, large

gate-charge increases the switching interval, tSW which

increases the MOSFET switching losses. Ensure that both

MOSFETs are within their maximum junction temperature at

high ambient temperature by calculating the temperature

rise according to package thermal-resistance specifications.

A separate heatsink may be necessary depending upon

MOSFET power, package type, ambient temperature and air

flow.

Approximate Losses while Sourcing current

PUPPER

Io2

(ON)

1--

VIN

PLOWER = Io2 x rDS(ON) x (1 - D)

Approximate Losses while Sinking current

PUPPER = Io2 x rDS(ON) x D

(EQ. 10)

PLOWER

rDS(ON)

1--

tSW

Where: D is the duty cycle = VOUT/VIN,

tSW is the combined switch ON and OFF time, and

fs is the switching frequency.

MOSFET Selection - LDO

The main criteria for selection of the linear regulator pass

transistor is package selection for efficient removal of heat.

Select a package and heatsink that maintains the junction

temperature below the rating with a maximum expected

ambient temperature.

The power dissipated in the linear regulator is:

PLINEAR â IO Ã (VIN â VOUT)

(EQ. 11)

where IO is the maximum output current and VOUT is the

nominal output voltage of the linear regulator.

FN9143.5

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