ISL6530 Datasheet, PDF (7/17 Pages) Intersil Corporation – Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination

ISL6530
While the V_TT supply “floats”, it is held to about 50% of
V_DDQ via a low current window regulator which drives V_TT
via the SENSE2 pin. The window regulator can overcome up
to at least ±10mA of leakage on V_TT.
While V2_SD is high, PGOOD is low.
PHASE1 and PHASE2
Connect PHASE1 and PHASE2 to the corresponding upper
MOSFET source. This pin is used as part of the upper
MOSFET bootstrapped drives. PHASE1 is used to monitor
the voltage drop across the upper MOSFET of the V_DDQ
regulator for over-current protection. The PHASE1 pin is
monitored by the adaptive shoot through protection circuitry
to determine when the upper FET of the V_DDQ supply has
turned off.
FB1, COMP1, FB2, and COMP2
COMP1, COMP2, FB1, and FB2 are the available external
pins of the error amplifiers. The FB1 and FB2 pins are the
inverting inputs of each error amplifier and the COMP1 and
COMP2 pins are the associated outputs. An appropriate AC
network across these pins is used to compensate the
voltage-controlled feedback loop of each converter.
VREF and VREF_IN
VREF produces a voltage equal to one half of the voltage on
SENSE1. This low current output is connected to the VREF
input of the DDRAM devices being powered. This same
voltage is used as the reference input of the V_TT error
amplifier. Thus V_TT is controlled to 50% of V_DDQ.
VREF_IN is used as an option to overdrive the internal
resistor divider network that sets the voltage for both
VREF_OUT and the reference voltage for the V_TT supply. A
100pF capacitor between VREF_IN and ground is
recommended for proper operation.
PVCC1
This is the positive supply for the lower gate driver, LGATE1.
PVCC1 is connected to a well decoupled 5V.
SENSE1 and SENSE2
Both SENSE1 and SENSE2 are connected directly to the
regulated outputs of the V_DDQ and V_TT supplies,
respectively. SENSE1 is used as an input to create the
voltage at VREF_OUT and the reference voltage for the V_TT
supply. SENSE2 is used as the regulation point for the
window regulator that is enabled in V2_SD mode.
Functional Description
Overview
The ISL6530 contains control and drive circuitry for two
synchronous buck PWM voltage regulators. Both regulators
utilize 5V bootstrapped output topology to allow use of low
cost N-channel MOSFETs. The regulators are driven by
300kHz clocks. The clocks are phase locked and displaced
90^o to minimize noise coupling between the controllers.
The first regulator includes a precision 0.8V reference and is
intended to provide the proper V_DDQ to a DDRAM memory
system. The V_DDQ controller implements overcurrent
protection utilizing the r_DS(ON) of the upper MOSFET.
Following a fault condition, the V_DDQ regulator is softstarted
via a digital softstart circuit.
Included in the ISL6530 is a precision V_REF reference
output. V_REF is a buffered representation of .5xV_DDQ. V_REF
is derived via a precision internal resistor divider connected
to the SENSE1 terminal.
The second PWM regulator is designed to provide V_TT
termination for the DDRAM signal lines. The reference to the
V_TT regulator is V_REF. Thus the V_TT regulator provides a
termination voltage equal to .5xV_DDQ. The drain of the upper
MOSFET of the V_TT supply is connected to the regulated
V_DDQ voltage. The V_TT controller is designed to enable both
sinking and sourcing current on the V_TT rail.
Two benefits result from the ISL6530 dual controller
topology. First, as VREF is always .5xV_DDQ, the V_TT supply
will track the V_DDQ supply during softstart cycles. Second,
the overcurrent protection incorporated into the V_DDQ supply
will simultaneously protect the V_TT supply.
Initialization
The ISL6530 automatically initializes upon application of
input power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage at the VCC pin. The
POR function initiates soft-start operation after the 5V bias
supply voltage exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft start sequence. The
PWM error amplifier reference input for the VDDQ regulator is
clamped to a level proportional to the soft-start voltage. As the
soft-start voltage slews up, the PWM comparator generates
PHASE pulses of increasing width that charge the output
capacitor(s). This method provides a rapid and controlled
output voltage rise. The soft start sequence typically takes
about 7ms.
With the V_TT regulator reference held at
1_--
2
⋅
V_DDQ
it
will
automatically track the ramp of the V_DDQ softstart, thus
enabling a soft-start for V_TT.
Figure 2 shows the soft-start sequence for a typical application.
At t0, the +5V VCC bias voltage starts to ramp. Once the
voltage on VCC crosses the POR threshold at time t1, both
outputs begin their soft-start sequence. The triangle waveforms
from the PWM oscillators are compared to the rising error
amplifier output voltage. As the error amplifier voltage
increases, the pulse-widths on the UGATE pins increase to
reach their steady-state duty cycle at time t2.
7
FN9052.2
November 15, 2004