ISL6530 Datasheet, PDF (6/17 Pages) Intersil Corporation – Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination

Functional Pin Description
24 LEAD (SOIC)
TOP VIEW
UGATE1 1
BOOT1 2
PHASE1 3
VREF 4
FB1 5
COMP1 6
SENSE1 7
VREF_IN 8
GNDA 9
PHASE2 10
BOOT2 11
UGATE2 12
24 _PGND1
23 LGATE1
22 PVCC1
21 OCSET/SD
20 V2_SD
19 PGOOD
18 COMP2
17 SENSE2
16 FB2
15 VCC
14 LGATE2
13 PGND2
ISL6530
32 LEAD (QFN)
TOP VIEW
32 31 30 29 28 27 26 25
PHASE 1 1
24 PVCC1
VREF 2
23 OCSET/SD
FB1 3
22 V2_SD
COMP1 4
21 PGOOD
SENSE1 5
20 COMP2
VREF_IN 6
19 SENSE2
GNDA 7
18 FB2
GNDA 8
17 VCC
9 10 11 12 13 14 15 16
BOOT1 and BOOT2
These pins provide bias voltage to the upper MOSFET
drivers. A single capacitor bootstrap circuit may be used to
create a BOOT voltage suitable to drive a standard N-
Channel MOSFET.
UGATE1 and UGATE2
Connect UGATE1 and UGATE2 to the corresponding upper
MOSFET gate. These pins provide the gate drive for the
upper MOSFETs. UGATE2 is also monitored by the adaptive
shoot through protection to determine when the upper FET
of the V_TT regulator has turned off.
LGATE1 and LGATE2
Connect LGATE1 and LGATE2 to the corresponding lower
MOSFET gate. These pins provide the gate drive for the
lower MOSFETs. These pins are monitored by the adaptive
shoot through protection to determine when the lower FET
has turned off.
PGND1 and PGND2
These are the power ground connections for the gate drivers
of the PWM controllers. Tie these pins to the ground plane
through the lowest impedence connection available.
OCSET/SD
A resistor (R_OCSET) connected from this pin to the drain of
the upper MOSFET of the V_DDQ regulator sets the
overcurrent trip point. R_OCSET, an internal 40µA current
source (I_OCS), and the upper MOSFET on-resistance
(r_DS(ON)) set the V_DDQ converter over-current (OC) trip
point according to the following equation:
I_PEAK
=
I_{--O-----C----S-----}•_----R_{-----O----C-----S----E---T--}
r_DS(ON)
An overcurrent trip cycles the soft-start function.
Pulling the OCSET/SD pin to ground resets the ISL6530 and
all external MOSFETS are turned off allowing the two output
voltage power rails to float.
PGOOD
A high level on this open-drain output indicates that both the
V_DDQ and V_TT regulators are within normal operating
voltage ranges.
GNDA
Signal ground for the IC. Tie this pin to the ground plane
through the lowest impedence connection available.
VCC
The 5V bias supply for the chip is connected to this pin. This
pin is also the positive supply for the lower gate driver,
LGATE2. Connect a well decoupled 5V supply to this pin.
V2_SD
A high level on the V2_SD input places the V2 controller into
“sleep” mode. In sleep mode, both UGATE2 and LGATE2
are driven low, effectively floating the V_TT supply.
6
FN9052.2
November 15, 2004