ISL55141 Datasheet, PDF (7/7 Pages) Intersil Corporation – Evaluation Board User’s Manual

Application Note 1270
ISL55143IRZ Evaluation Board Schematic
QA0_J3
QA0
TP01-QA0_VOL
R1
DIF+
50Ω
DIF--
QB0_J4
QB0
TP02-QB0_VOL
DIF+
R2
50Ω
DIF--
QA1_J18
QA1
TP03-QA1_VOL
R12
DIF+
50Ω
DIF--
QB1_J21
QB1
TP05-QB1_VOL
R16
50Ω
DIF+
QA0
QB0
DIF--
QA1
QB1
QA2_J17
QA2
TP05-QA3_VOL
QA2
R11
DIF+
50Ω
QB2
QA3
DIF--
QB3
QB2_J21
QB2
TP06-QB2_VOL
DIF+
R15
50Ω
DIF--
QA3_J12
QA3
TP07-QA3_VOL
DIF+
R6
50Ω
DIF--
VINP0
S1 - POWER-DOWN CONTROL
SPDT - CENTER OFF
VEE
VDD
PD - BN_J5
VCC
2
3
4
5
6
7
8
9
QA0
QB0
QA1
QB1
QA2
QB2
QA3
QB3
ISL55143_QFN
GND
VEE
VINP0
CVB0
VINP0
CVA0
CVB1
VINP1
CVA1
CVB2
VINP2
CVA2
27
26
25
24
23
22
21
20
19
CVB_BUS
VINP1
VINP2
TP10-VINP0
DIF+
DIF--
VINP1
TP10-VINP1
DIF+
DIF--
VINP2
TP10-VINP2
DIF+
DIF--
VINP3
TP10-VINP3
DIF+
DIF--
R18
R14
VINP0_J16
0Ω
0Ω
R20
NOT POPULATED
GND
GND
R8
R10
VINP1_J15
0Ω
0Ω
R9
NOT POPULATED
GND
GND
R4
R6
0Ω
0Ω
VINP2_J14
C9
NOT POPULATED
GND
GND
R3
R5
0Ω
0Ω
VINP3_J8
R4
NOT POPULATED
GND
CVB_BUS
GND
TP16_CVB
DIF+
CVB_BUS
C5
0.1µF
C7
+4.7µF
J9-CVB - Banana Jack
DIF--
GND
VOH
VCC
JP01
VOL = VEE
JP02
JP03
VOL = GND VEE = GND
CVA_BUS
VINP3
CVA_BUS
TP15_CVA
DIF+
CVA_BUS
C6
0.1µF
DIF--
GND
TP01_VCC_VEE
VCC
C4 C3 C9
+4.7µF 0.1µF 0.1µF
GND
C8
+4.7µF
GND
J10-GND - Banana Jack
J11-CVA - Banana Jack
QB3_J13
QB3
R7
50Ω
VOL
TP08-QB3_VOL
DIF+
DIF--
VOL - Banana Jack
VOH - Banana Jack
GND
VEE
GND
VOH
TP03-VOH_VOL
C1 C2
DIF+
+4.7µF 0.1µF
DIF--
VOL
GND - Banana Jack VCC - Banana Jack VEE - Banana Jack
FIGURE 10. ISL55143IRZ QFN QUAD COMPARATOR EVALUATION BOARD
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
AN1270.0
September 27, 2006