ISL55141 Datasheet, PDF (2/7 Pages) Intersil Corporation – Evaluation Board User’s Manual

Application Note 1270
Scope Probe Connections
Another topic to cover before getting started is the evaluation
board physical connections for waveform observations. On
each schematic version you will see a component with pins
designated as DIF+ and DIF-. This is not an active
component but a dual pin header physically design to
accommodate connection of active differential probes. This
will minimize ground lead inductance and capacitive loading
while make waveform observations. However, the user must
also be mindful of max voltage limitations when using these
types of probes. The ISL5514x comparators cover a large
voltage range, so double check the probe’s specifications.
SCOPE PROBE CONNECTIONS
DIF+
DIF--
QA_J3
QA0
R1
50Ω
VOL
TP01-QA_VOL
DIF+
DIF--
TP07-VINP
R18
0Ω
DIF+
R14
VINP_J8
0Ω
DIF--
R20
NOT POPULATED
GND
GND
FIGURE 3. DUAL1” SPACED PINS ARE PLACED ON THE
EVALUATION BOARDS FOR DIFFERENTIAL
PROBE CONNECTIONS
Scope probe test points (TP) are positioned across all
inputs, outputs and VCC and VEE.
BNC Connections
This series of evaluation boards also provides BNC
connections for input and output signals. A key point to
remember is the ISL55141, ISL55142, ISL55143 comparator
outputs (QA/QB) operate with the VOH voltage as a High
and VOL voltage as a Low. QA/QB BNC’s, which are
connected to the outputs, have the shield connected to the
VOL voltage bus. Keep this in mind when making BNC
connections to avoid connecting the GND shield of the BNC
inputs to the VOL shield of the BNC outputs.
Also note that the comparator outputs have 50Ω
terminations that you may need to remove for your
application.
QA_J3
QA0
TP01-QA_VOL
QB_J4
DIF+
R1
50Ω
DIF--
1 _{VEE PD} 14
VOL
QB0
TP02-QB_VOL
QA0
QB0
VOL
VOH
4
5
6
7
QA
QB
VOL
VOH
CVB
VINP
CVA
VCC
VEE
12
11
10
9
8
R2
DIF+
50Ω
DIF--
VOL
ISL55141_TSSOP
FIGURE 4. BNC CONNECTIONS ON THE QA/QB
COMPARATOR OUTPUTS HAVE THE SHIELD
CONNECTED TO THE VOL BUS. NOTE: YOU MAY
WISH TO REMOVE THE 50Ω TERMINATIONS.
VINP
TP07-VINP
R18
0Ω
DIF+
DIF--
R14
VINP_J8
0Ω
R20
NOT POPULATED
GND
PD ¹⁴
GND
CVB
VINP
CVA
VCC
VEE
12 CVB_BUS
11
VINP
10 CVA_BUS
9
VCC
8
VEE
_TSSOP
FIGURE 5. BNC CONNECTIONS ON THE HIGH SPEED VINP
PINS HAVE THE SHIELD CONNECTED TO GND.
NOTE: TWO SMD SERIES POSITIONS PLUS ONE
POSITION TO GROUND ARE AVAILABLE FOR
USER SPECIFIC CIRCUITRY.
Power-Down Feature
All boards provide the same capability for testing the
power-down feature. A SPDT- center OFF switch is provided
for manual testing of the feature. In one position the PD input
is connected to VCC (Power-down enabled). In the other
position the PD Input is connected to VEE (power-down
disabled).
S1 - POWER-DOWN CONTROL
SPDT - CENTER OFF
VEE
VDD
PD - BN_J5
PD
GND
1 _{VEE PD} 14
4
5
6
7
QA
QB
VOL
VOH
CVB
VINP
CVA
VCC
VEE
12
11
10
9
8
ISL55141_TSSOP
FIGURE 6. ALL ISL5514X EVALUATION BOARDS HAVE THE
SAME POWER-DOWN CIRCUITRY.
2
AN1270.0
September 27, 2006