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ISL54400 Datasheet, PDF (7/15 Pages) Intersil Corporation – Low Voltage, Dual SPDT, USB/Audio Switches with Negative Signal Capability
ISL54400, ISL54401, ISL54402
Electrical Specifications - 2.7V to 5.5V Supply Test Conditions: VDD = +3.0V, GND = 0V, VBUSH = 3.8V, VBUSL = 3.2V,
VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
TEMP (NOTE 5)
(NOTE 5)
(°C)
MIN
TYP
MAX UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range, VDD
(ISL54400 and ISL54401 only)
Full
2.5
-
3.6
V
Power Supply Range, VDD
(ISL54402 Only)
Full
1.8
-
5.5
V
Positive Supply Current, IDD
Audio Mode
(ISL54400 and ISL54401 only)
VDD = 3.6V, VBUS = Float
25
-
Full
-
4.5
8
µA
-
10
µA
Positive Supply Current, IBUS
USB Mode
(ISL54400 and ISL54401 only)
VDD = 3.6V, VBUS = 5.25V
25
-
Full
-
3.5
8
µA
-
25
µA
Positive Supply Current, IDD
(ISL54402 Only)
VDD = 5.5V, VIN = 0V
25
-
Full
-
8
11
µA
-
15
µA
Positive Supply Current, IDD
(ISL54402 Only)
VDD = 5.5V, VIN = 5.5V
25
-
0.06
0.5
µA
Full
-
-
1
µA
Positive Supply Current, IDD
(ISL54402 Only)
VDD = 5.5V, VIN = 2.85V
25
-
Full
-
5.5
8
µA
-
10
µA
VTERM Voltage, VVTERM
(ISL54400 Only)
VDD = 2.5V, VBUS = 4.4V, RTERM = 16.5kΩ to Ground
25
3.0V
-
3.6V
V
VTERM Voltage, VVTERM
(ISL54400 Only)
VDD = 2.0V, VBUS = 4.4V
25
-1.4
-
0.5
V
DIGITAL INPUT CHARACTERISTICS
VBUS Voltage Low, VBUSL
(ISL54400 and ISL54401 Only)
Full
-
-
VDD + 0.2 V
VBUS Voltage High, VBUSH
(ISL54400 and ISL54401 Only)
Full VDD + 0.8
-
-
V
Input Voltage Low, VINL
(ISL54402 Only)
VDD = 2.7V to 3.6V
Full
-
-
0.5
V
Input Voltage High, VINH
(ISL54402 Only)
VDD = 2.7V to 3.6V
Full
1.4
-
-
V
Input Voltage Low, VINL
(ISL54402 Only)
VDD = 5.0V
Full
-
-
0.8
V
Input Voltage High, VINH
(ISL54402 Only)
VDD = 5.0V
Full
2.3
-
-
V
Input Current, IINH, IINL
(ISL54402 Only)
VDD = 5.5V, VIN = 0V or VDD
Full
-
0.1
-
µA
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Guaranteed by design.
9. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max
RON value, between L and R, between NC1 and NC2 or between D+ and D-, or between NO1 and NO2.
7
FN6240.3
July 12, 2006