ISL54050_14 Datasheet, PDF (7/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.65V to +4.5V,Single Supply, Dual SPDT Analog Switch

ISL54050
Test Circuits and Waveforms (Continued)
V+
C
SIGNAL
GENERATOR
NO OR NC
ANALYZER
R_L
IN 0V or V+
COM
GND
r_ON = V₁/100mA
NO OR NC
V_NX
100mA
V₁
V+
C
0V OR V+
IN
COM
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
Repeat test for all switches.
FIGURE 5. r_ON TEST CIRCUIT
SIGNAL
GENERATOR
V+
C
NO OR NC
COM
50Ω
IN₁
0V or V+
ANALYZER
R_L
COM
NC OR NO
GND
N.C.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54050 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
ON-resistance (0.29Ω) and high speed operation
(t_ON = 40ns, t_OFF = 20ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(4.5µW max), low leakage currents (195nA max), and the tiny
µTQFN package. The ultra low ON-resistance and r_ON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL54050 IC (see Figure 8).
7
IMPEDANCE
ANALYZER
V+
C
NO OR NC
IN 0V OR V+
COM
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation, the sub-microamp I_DD current of
the IC produces an insignificant voltage drop across the
100Ω series resistor resulting in no impact to switch
operation or performance.
FN6356.4
November 22, 2008