ISL54050_14 Datasheet, PDF (5/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.65V to +4.5V,Single Supply, Dual SPDT Analog Switch

ISL54050
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V_INH = 1.4V, V_INL = 0.5V (Note 4),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 5, 8) TYP (Notes 5, 8) UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, V_IN = 0V or V+
25
0.01
µA
Full
0.52
µA
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V_INL
Input Voltage High, V_INH
Input Current, I_INH, I_INL
V+ = 3.3V, V_IN = 0V or V+ (Note 9)
25
25
1.4
Full
-0.5
0.5
V
V
0.5
µA
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, V_INH = 1.0V, V_INL = 0.4V (Note 4),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 5, 8) TYP (Notes 5, 8) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V_ANALOG
Full
0
ON-Resistance, r_ON
V+ = 1.65V, I_COM = 100mA, V_NO or V_NC = 0V to V+ 25
(see Figure 5)
Full
V+
V
0.7
0.8
Ω
0.85
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, t_ON
V+ = 1.65V, V_NO or V_NC = 1.0V, R_L = 50Ω, C_L = 35pF 25
70
ns
(see Figure 1)
Full
80
ns
Turn-OFF Time, t_OFF
V+ = 1.65V, V_NO or V_NC = 1.0V, R_L = 50Ω, C_L = 35pF 25
54
ns
(see Figure 1)
Full
65
ns
Break-Before-Make Time Delay, t_d V+ = 2.0V, V_NO or V_NC = 1.0V, R_L = 50Ω, C_L = 35pF Full
10
ns
(see Figure 3)
Charge Injection, Q
C_L = 1.0nF, V_G = 0V, R_G = 0Ω (see Figure 2)
25
42
pC
NO or NC OFF Capacitance, C_OFF f = 1MHz, V_NO or V_NC = V_COM = 0V (see Figure 7) 25
70
pF
COM ON Capacitance, C_COM(ON) f = 1MHz, V_NO or V_NC = V_COM = 0V (see Figure 7) 25
186
pF
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V_INL
25
0.4
V
Input Voltage High, V_INH
25
1.0
V
Input Current, I_INH, I_INL
V+ = 2.0V, V_IN = 0V or V+ (Note 9)
Full
-0.5
0.5
µA
NOTES:
4. V_IN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. r_ON matching between channels is calculated by subtracting the channel with the highest max r_ON value from the channel with lowest max r_ON
value, between NC1 and NC2 or between NO1 and NO2.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Limits established by characterization and are not production tested.
5
FN6356.4
November 22, 2008