ISL54050_14 Datasheet, PDF (6/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.65V to +4.5V,Single Supply, Dual SPDT Analog Switch

ISL54050
Test Circuits and Waveforms
V+
LOGIC
INPUT
0V
50%
t_OFF
t_r < 5ns
t_f < 5ns
SWITCH
INPUT
V_NO
SWITCH
OUTPUT _0V
V_OUT
90%
t_ON
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
C
SWITCH
INPUT
LOGIC
INPUT
NO OR NC
IN
GND
COM
V_OUT
R_L
C_L
50Ω 35pF
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V(NO _{or NC)}
-----------^R-----^L------------
R_L + r_(ON)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
FIGURE 1B. TEST CIRCUIT
V+
C
SWITCH
OUTPUT
V_OUT
LOGIC ^ON
INPUT
ΔV_OUT
OFF
Q = ΔV_OUT x C_L
V+
ON
0V
R_G
NO OR NC
COM
V_G
GND
IN
LOGIC
INPUT
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V_OUT
C_L
V+
LOGIC
INPUT
0V
SWITCH
OUTPUT
V_{OUT 0V}
V+
C
90%
NO
V_NX
NC
IN
COM
V_OUT
R_L
C_L
50Ω
35pF
LOGIC
GND
t_D
INPUT
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. C_L includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6356.4
November 22, 2008