ISL43L110 Datasheet, PDF (7/11 Pages) Intersil Corporation – Ultra Low ON-Resistance, +1.1V to +4.5V Single Supply, SPST Analog Switches

ISL43L110, ISL43L111
Test Circuits and Waveforms (Continued)
V+
C
SIGNAL
GENERATOR
NO or NC
IN 0V or V+
R_ON = V₁/100mA
NO or NC
V_NX
100mA
V₁
V+
C
0V or V+
IN
ANALYZER
R_L
COM
GND
COM
GND
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. R_ON TEST CIRCUIT
IMPEDANCE
ANALYZER
NO or NC
V+
C
IN 0V or V+
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43L110 and ISL43L111 are bidirectional, single
pole/single throw (SPST) analog switches. They offer
precise switching capability from a single +1.1V to 4.5V
supply with ultra low on-resistance and high speed
operation. With a single supply of 4.3V the typical on-
resistance is only 0.21Ω, with a typical turn-on and turn-off
time of: t_ON = 8ns, t_OFF = 5ns. The devices are especially
well suited for portable battery powered equipment due to its
low operating supply voltage (1.1V), low power consumption
(1.8µW max), low leakage currents (200nA max), and the tiny
SC70 packaging.
The ISL43L110 is a normally open (NO) SPST analog
switch. The ISL43L111 is a normally closed (NC) SPST
analog switch.
7
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 6). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the input (see Figure 6). The resistor limits the
input current below the threshold that produces permanent
FN6130.0
March 15, 2005