ISL43410 Datasheet, PDF (7/13 Pages) Intersil Corporation – Low-Voltage, Single Supply, DPDT High Low-Voltage, Single Supply, DPDT High

ISL43410
Test Circuits and Waveforms (Continued)
3V
LOGIC
INPUT
0V
SWITCH
OUTPUT
0V
50%
t_TRANS
90% ^VOUT
t_r < 20ns
t_f < 20ns
90%
C
V+
LOGIC
INPUT
V+
C
NC
NO
ADD
COM
GND INH
V_OUT
R_L
300Ω
C_L
35pF
t_TRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V(NO _{or NC)}
---------^R-----^L---------
R_L + r_ON
FIGURE 1C. ADDRESS MEASUREMENT POINTS
FIGURE 1D. ADDRESS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
LOGIC ^OFF
INPUT
ON
SWITCH
OUTPUT
V_OUT
Q = ΔV_OUT x C_L
3V
OFF
0V
ΔV_OUT
V+
C
R_G
NO or NC
COM
ADD
V_G
GND INH
LOGIC
INPUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
V_OUT
C_L
3V
LOGIC
INPUT
0V
t_r < 20ns
t_f < 20ns
C
V+
V+
C
NO
COM
V_OUT
NC
R_L
C_L
300Ω
35pF
SWITCH
OUTPUT
V_OUT
0V
80%
t_D
LOGIC
INPUT
ADD
GND INH
Repeat test for other switches. C_L includes fixture and stray
capacitance.
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
7
FN6044.4
May 12, 2008