ISL43410 Datasheet, PDF (6/13 Pages) Intersil Corporation – Low-Voltage, Single Supply, DPDT High Low-Voltage, Single Supply, DPDT High

ISL43410
Electrical Specifications + 12V Supply Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, V_INH = 4V, V_INL = 0.8V (Note 6),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 7, 12) TYP (Notes 7, 12) UNITS
DYNAMIC CHARACTERISTICS
Inhibit Turn-ON Time, t_ON
V+ = 10.8V, V_NO or V_NC = 10V, R_L = 300Ω, C_L = 35pF 25
-
25
-
ns
V_IN = 0 to 4, (see Figure 1)
Full
-
30
-
ns
Inhibit Turn-OFF Time, t_OFF
V+ = 10.8V, V_NO or V_NC = 10V, R_L = 300Ω, C_L = 35pF 25
-
24
-
ns
V_IN = 0 to 4, (see Figure 1)
Full
-
30
-
ns
Address Transition Time, t_TRANS V+ = 10.8V, V_NO or V_NC = 10V, R_L = 300Ω, C_L = 35pF 25
-
35
-
ns
V_IN = 0 to 4, (see Figure 1)
Full
-
50
-
ns
Break-Before-Make Time Delay, t_D V+ = 13.0V, R_L = 300Ω, C_L = 35pF, V_NO or V_NC = 10V Full
-
9
-
ns
V_IN = 0 to 4 (see Figure 3)
Charge Injection, Q
C_L = 1.0nF, V_G = 0V, R_G = 0Ω (see Figure 2)
25
-
1.2
-
pC
OFF-Isolation
R_L = 50Ω, C_L = 5pF, f = 1MHz, (see Figure 4)
25
-
75
-
dB
Crosstalk (Channel-to-Channel) R_L = 50Ω, C_L = 5pF, f = 1MHz, (see Figure 6)
25
-
-85
-
dB
NO or NC OFF Capacitance, C_OFF f = 1MHz, V_NO or V_NC = V_COM = 0V, (see Figure 7)
25
-
4
-
pF
COM OFF Capacitance,
C_COM(OFF)
f = 1MHz, V_NO or V_NC = V_COM = 0V, (see Figure 7)
25
-
6
-
pF
COM ON Capacitance, C_COM(ON) f = 1MHz, V_NO or V_NC = V_COM = 0V, (see Figure 7)
25
-
12
-
pF
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 13.0V, V_IN = 0V or V+, all channels on or off
Full
-1
0.0001
1
µA
NOTES:
6. V_IN = input voltage to perform proper function.
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C.
9. Δr_ON = r_ON (MAX) - r_ON (MIN).
10. Flatness is defined as the difference between the maximum and minimum value of ON-resistance over the specified analog signal range.
11. Limits established by characterization and are not production tested.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Test Circuits and Waveforms
3V
LOGIC
INPUT
0V
50%
t_ON
SWITCH
OUTPUT _0V
t_OFF
90% ^VOUT
t_r < 20ns
t_f < 20ns
90%
C
V+
LOGIC
INPUT
V+
C
NC
NO
COM
INH
GND ADD
V_OUT
R_L
300Ω
C_L
35pF
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for other switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V(NO _{or NC)}
---------^R-----^L---------
R_L + r_ON
FIGURE 1B. TEST CIRCUIT
6
FN6044.4
May 12, 2008