ISL267452 Datasheet, PDF (7/16 Pages) Intersil Corporation – 12-Bit, 555kSPS SAR ADC

ISL267452
Timing Specifications Limits established by characterization and are not production tested. VDD = 3.0V to 3.6V, f_SCLK = 10MHz,
f_S = 555kSPS, VREF = 2.0V; VDD = 4.75V to 5.25V, f_SCLK = 10MHz, f_S = 555kSPS, VREF = 2.5V; V_CM = VREF unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNITS
f_SCLK
t_SCLK
t_ACQ
t_CONV
t_CSW
t_CSS
t_CDV
t_CLKDV
t_SDH
t_SW
t_DISABLE
Clock Frequency
Clock Period
Acquisition Time
Conversion Time
CS Pulse Width
CS Falling Edge to S_CLK Falling Edge Setup Time
CS Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Hold
SCLK Pulse Width
SCLK Falling Edge to SDATA Disable Time
(Note 9)
Extrapolated back to true bus relinquish
0.01
100
10
10
10
0.4 x t_SCLK
10
10
MHz
ns
200
ns
1.6
µs
ns
ns
20
ns
40
ns
ns
ns
35
ns
t_QUIET Quiet Time Before Sample
60
ns
NOTE:
9. During characterization, t_DISABLE is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the AD7452
loading (25pF) is calculated.
CS
tCSS
SCLK
tCDV
SDATA
1
0
0
2
3
tCLKDV
0
0
tCONV
4
5
tSW
MSB
13
14
15
16
tACQ
D2
D1
D0
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85kΩ
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
tCSW
tQUIET
HI-Z
7
FN8255.0
July 26, 2012