ISL267452 Datasheet, PDF (13/16 Pages) Intersil Corporation – 12-Bit, 555kSPS SAR ADC

ISL267452
FIGURE 28. ISL267452 SYSTEM TIMING
Power-On Reset
When power is first applied, the ISL267452 performs a power-on
reset that requires approximately 2.5ms to execute. After this is
complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track
and hold. The dummy conversion cycle will take 1.6µs with an
10MHz SCLK. Once the dummy cycle is complete, the ADC mode
will be determined by the state of CS. Regular conversions can be
started immediately after this dummy cycle is completed and
time has been allowed for proper acquisition.
Acquisition Time
To achieve the maximum sample rate (555kSps) in the
ISL267452 device, the maximum acquisition time is 200ns. For
slower conversion rates, or for conversions performed using a
slower SCLK value than 10MHz, the minimum acquisition time is
200ns. This minimum acquisition time also applies to all the
devices if short cycling is utilized.
Short Cycling
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all SCLK falling edges have elapsed.
This is referred to as short cycling, and it can be used to further
optimize power dissipation. In this mode, a lower resolution
result will be output, but the ADC will enter static mode sooner
and exhibit a lower average power consumption than if the
complete conversion cycle were carried out. The minimum
acquisition time (t_ACQ) requirement of 200ns must be met for
the next conversion to be valid.
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL267452 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267452 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267452 to avoid
noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
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FN8255.0
July 26, 2012