ISL267452 Datasheet, PDF (12/16 Pages) Intersil Corporation – 12-Bit, 555kSPS SAR ADC

ISL267452
100
10
VDD = 5V
1
VDD = 3V
0.1
0.01
0
50
100 150 200 250 300 350
THROUGHPUT (kSPS)
FIGURE 25. POWER CONSUMPTION vs THROUGHPUT RATE
5V
0.1µF
+ ^BULK
1 DNC DNC 8
2 V_IN
DNC 7
3 COMP V_OUT 6
2.5V
4 GND TRIM 5
ISL21090
VDD
ISL267452
VREF
0.1µF
0.1µF
FIGURE 26. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+3.0V TO +3.6V
OR +5V
V_IN 1
V_OUT 2
GND
3
ISL21010
+
BULK
0.1µF
VDD
ISL267452
VREF
1.25, 2.048 OR 2.5V
0.1µF
0.1µF
FIGURE 27. VOLTAGE REFERENCE FOR +3.0V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
The ISL267452 is designed to minimize power consumption by
only powering up the SAR comparator during conversion time.
When the converter is in track mode (its sample capacitors are
tracking the input signal) the SAR comparator is powered down.
The state of the converter is dictated by the logic state of CS.
When CS is high, the SAR comparator is powered down while the
sampling capacitor array is tracking the input. When CS
transitions low, the capacitor array immediately captures the
analog signal that is being tracked. After CS is taken low, the
SCLK pin is toggled 16 times. For the first 3 clocks, the
comparator is powered up and auto-zeroed, then the SAR
decision process is begun. This process uses 12 SCLK cycles.
Each SAR decision is presented to the SDATA output on the next
clock cycle after the SAR decision is performed. The SAR process
(12 bits) is completed on SCLK cycle 15. At this point in time, the
SAR comparator is powered down and the capacitor array is
placed back into Track mode. The last SAR comparator decision
is output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
Figure 28 on page 13 illustrates the system timing for the
ISL267452.
12
FN8255.0
July 26, 2012