HCTS75MS Datasheet, PDF (7/9 Pages) Intersil Corporation – Radiation Hardened Dual 2-Bit Bistable Transparent Latch

HCTS75MS
Propagation Delay Timing Diagram and Load Circuit
VIH
VSS
VOH
VOL
VS
INPUT
TPLH
TPHL
VS
OUTPUT
DUT
50pF
TEST
500Ω
Transition Timing Diagram
VOH
VOL
TTLH
20%
80% 80%
OUTPUT
TTHL
20%
PARAMETER
VCC
VIH
VS
VIL
GND
VOLTAGE LEVELS
HCTS
4.50
3.00
1.30
0
0
UNITS
V
V
V
V
V
Pulse Width, Setup, Hold Timing Diagram and Load Circuit
D INPUT
VIH
VS
VIL
E INPUT
VIH
VIL
TH
TSU
TW
VS
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
DUT
50pF
TEST
500Ω
PARAMETER
VCC
VIH
VS
VIL
GND
VOLTAGE LEVELS
HCTS
4.50
4.50
2.25
0
0
UNITS
V
V
V
V
V
Pulse Width, Setup, Hold Timing Diagram Negative Edge Trigger and Load Circuit
INPUT
VIH
VS
VIL
INPUT CP
VIH
VIL
TW
TH
TSU
TW
VS
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
DUT
50pF
TEST
500Ω
PARAMETER
VCC
VIH
VS
VIL
GND
VOLTAGE LEVELS
HCTS
4.50
4.50
2.25
0
0
UNITS
V
V
V
V
V
Spec Number 518625
476