HCTS75MS Datasheet, PDF (1/9 Pages) Intersil Corporation – Radiation Hardened Dual 2-Bit Bistable Transparent Latch

HCTS75MS
September 1995
Radiation Hardened
Dual 2-Bit Bistable Transparent Latch
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit
bistable transparent latch. Each of the two latches are controlled
by a separate enable input (E) which are active low. E low latches
the output state.
The HCTS75MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS75MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
HCTS75DMSR
HCTS75KMSR
HCTS75D/
Sample
HCTS75K/
Sample
HCTS75HMSR
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
-55^oC to +125^oC Intersil Class
S Equivalent
16 Lead SBDIP
-55^oC to +125^oC Intersil Class 16 Lead Ceramic
S Equivalent Flatpack
+25^oC
Sample
16 Lead SBDIP
+25^oC
+25^oC
Sample
Die
16 Lead Ceramic
Flatpack
Die
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
Q0 1 1
D0 1 2
D1 1 3
E2 4
VCC 5
D0 2 6
D1 2 7
Q1 2 8
16 1 Q0
15 1 Q1
14 1 Q1
13 1 E
12 GND
11 2 Q0
10 2 Q0
9 2 Q1
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Q0 1
D0 1
D1 1
E2
VCC
D0 2
D1 2
Q1 2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1 Q0
1 Q1
1 Q1
1E
GND
2 Q0
2 Q0
2 Q1
Functional Diagram
2(6)
D0
13(4)
E
LATCH 0
D
Q
LE LE
16(10
1(11
14(8
3(7)
D1
LE LE
D
Q
15(9
5 VCC
12 _GND
LATCH 1
TRUTH TABLE
INPUTS
D
E
L
H
H
H
X
L
OUTPUTS
Q
Q
L
H
H
L
Q0
Q0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
470
Spec Number 518625
File Number 3189.1