HC5517_00 Datasheet, PDF (7/19 Pages) Intersil Corporation – 3 REN Ringing SLIC For ISDN Modem/TA and WLL

HC5517
AC Voltage Gain Design Equations
The HC5517 uses feedback to synthesize the impedance at
the 2-wire tip and ring terminals. This feedback network
defines the AC voltage gains for the SLIC.
The 4-wire to 2-wire voltage gain (V_RX to V_TR) is set by the
feedback loop shown in Figure 3. The feedback loop senses
the loop current through resistors R₁₃ and R₁₄, sums their
voltage drop and multiplies it by 2 to produce an output voltage
at the V_TX pin equal to +4R_S∆I_L. The V_TX voltage is then fed
into the -IN1 input of the SLIC’s internal op amp. This signal is
multiplied by the ratio R₈/R₉ and fed into the tip current
summing node via the OUT1 pin. (Note: the internal V_BAT/2
reference (ring feed amplifier) and the internal +2V reference
(tip feed amplifier) are grounded for the AC analysis.)
The current into the OUT1 pin is equal to:
I_OUT1
=
–
4_----R_-----S----∆_----I_-L--
R
^RR-----89- 
(EQ. 5)
Equation 6 is the node equation for the tip amplifier summing
node. The current in the tip feedback resistor (I_R) is given in
Equation 7.
–
I_R
–
-⁴---^R-----_R^S----^∆----^I--^L-



RR_{-----89- }
+ -^V---_R-^R----^X--
=
0
(EQ. 6)
I_R
=
–
4_----R_-----RS----∆_---I_--L--



R^-R----89-_{}
+ -^V---_R-^R----^X--
The AC voltage at V_C is then equal to:
V_C = (I_R)(R)
(EQ. 7)
(EQ. 8)
V_C
=
–4
R_S
∆I_L



RR_{-----89- }
+
V_RX
(EQ. 9)
and the AC voltage at V_D is:
V_D
=
4
R_S
∆I_L



RR_{-----89- }
– V_RX
(EQ. 10)
The values for R₈ and R₉ are selected to match the
impedance requirements on tip and ring, for more
information reference AN9607 “Impedance Matching Design
Equations for the HC5509 Series of SLICs”. The following
loop current calculations will assume the proper R₈ and R₉
values for matching a 600Ω load.
The loop current (∆I_L) with respect to the feedback network,
is calculated in Equations 11 through 14. Where R₈ = 40kΩ,
R₉ = 40kΩ, R_L = 600Ω, R₁₁ = R₁₂ = R₁₃ = R₁₄ = 50Ω.
∆I_L = -_R----_L-----+----_R-----₁---₁----+-^V----^C_R-----₁^–---₂--^V--+--^D---_R-----₁---₃----+-----_R----₁---₄--
(EQ. 11)
IR
=
–_---4_-----(_--R_---R--S----∆_----I_-L-----)



RR_{-----89--}
+ ^V-----^RR----^X---
I_R
R
+ ^∆IL - + ^∆IL -
R₁₁
R₁₃
TIP
A
-
+
-
+ ^VC
R
V_RX
1V_P
OUT1
R
R/20
V_RING
R/2
VC
=
–4
RS∆IL



RR_{-----89--}
+ VRX
†
+_{- 2VDC}
I_OUT1 =
4R_S∆I_L
2R
R₈
R₉
-
V_{TR RL}
∆I_L
+
R₁₁ = R₁₂ = R₁₃ = R₁₄ = R_S
+R_S∆I_L
-
+
∆V_IN
+_-
-
∆I_L
+
B
R₁₂
RING
- ^∆IL +
R₁₄
- ^∆IL +
90kΩ 90kΩ
+
-
-R_S∆I_L
-
+
+
- ^VD
VD
=
4RS
∆I
L



RR_{-----89--}
– VRX
R₉
+
-
2
V_TX
+
4R_-S∆I_L
R₈
-IN₁
-
+
-
4R_S∆I_L
+
R₈
R₉
†
-
+
V_BAT
2
† GROUNDED FOR AC ANALYSIS
FIGURE 3. AC VOLTAGE GAIN AND IMPEDANCE MATCHING
7