HC5517_00 Datasheet, PDF (15/19 Pages) Intersil Corporation – 3 REN Ringing SLIC For ISDN Modem/TA and WLL

HC5517
Additional Tip and Ring Offset Voltage
A DC offset is required to level shift tip and ring from ground
and V_BAT respectively. By design, the tip amplifier is offset
4V below ground and the ring amplifier is offset 4V above
V_BAT . The 4V offset was designed so that the peak voice
signal could pass through the SLIC without distortion.
Therefore, to maintain distortion free transmission of pulse
metering and voice, an additional offset equal to the peak of
the pulse metering signal is required.
The tip and ring voltages are offset by a voltage divider network
on the V_RX pin. The V_RX pin is a unity gain input designed as
the 4-wire side voice input for the SLIC. Figure 13 details the
circuit used to generate the additional offset voltage.
+5V
R
-
+
2-WIRE SIDE
V_PMO
R
V_RX
R_{6 C7}
R₇
4-WIRE SIDE
C_{5 VOICE INPUT}
TO VOICE INPUT OF
TRANSHYBRID AMP
FIGURE 13. PULSE METERING OFFSET GENERATION
The amplifier shown is the tip amplifier. Other signals are
connected to the summing node of the amplifier but only those
components used for the offset generation are shown. The
offset generated at the output of the tip amplifier is summed at
the ring amplifier inverting input to provide a positive offset from
the battery voltage. The connection to the ring amplifier was
omitted from Figure 13 for clarity, refer to Figure 3 for details.
The term V_PMO is defined to be the offset required for the
pulse metering signal. The value of the offset voltage is
calculated as the peak value of the pulse metering signal.
Equation 45 assumes the amplitude of the pulse metering
signal is expressed as an RMS voltage.
V_PMO = 2 • V_PM
(EQ. 45)
The value of R₆ can be calculated from the following
equation:
R₆
=
^-R---R-7^{---7--+--R--R---}



5_{-----–V----P-}V_{---M-P----MO-----O--}
(EQ. 46)
The component labeled R is the internal summing resistor of
the tip amplifier and has a typical value of 108kΩ. The value
of R₇ should be selected in the range of 4.99kΩ and 10kΩ.
Staying within these limits will minimize the parallel loading
effects of the internal resistor R on R₇ as well as minimize
the constant power dissipation introduced by the divider.
Solving Equation 45 for 1V_RMS results in a 1.414V
requirement for V_PMO . Setting R₇ of Equation 46 to 10kΩ
and substituting the values for V_PMO and R yields 23.2kΩ
for R₆. The value of R₆ can be rounded to the nearest
standard value without significantly changing the offset
voltage.
Single Low Voltage Supply Operation
The application circuit shown Figure 15 requires 2 low
voltage supplies (+5V, -5V). The following application offers
away to make use of a 2.5V reference, provided with some
CODEC, to operate the transhybrid balance amplifier from
a single +5V supply. The implementation is shown in
Figure 14. Notice that the three inputs from the SLIC must all
be AC coupled to insure the proper DC gain through the
CODECs internal op amp. The resistor Ra is not used for
gain setting and is only intended to balance the DC offsets
generated by the input bias current of the CODEC amplifier.
If the DC offsets generated by the input bias currents are
negligible, then Ra may be omitted from the circuit. Ca may
be required for decoupling of the voltage reference pin and
does not contribute to the response of the amplifier.
0.1µF R₂
V_RX
0.1µF R₃
OUT₁
0.1µF R₄
V_PM
R₁
24.9kΩ
Ra
24.9kΩ
Ca
0.1µF
CODEC
-
+
2.4V
REF
FIGURE 14. SINGLE LOW VOLTAGE SUPPLY OPERATION
Layout Guidelines and Considerations
The printed circuit board trace length to all high impedance
nodes should be kept as short as possible. Minimizing length
will reduce the risk of noise or other unwanted signal pickup.
The short lead length also applies to all high gain inputs. The
set of circuit nodes that can be categorized as such are:
• V_RX pin 27, the 4-wire voice input.
• -IN1 pin 13, the inverting input of the internal amplifier.
• V_REF pin 3, the noninverting input to ring feed ampli-
fier.
• V_RING pin 24, the 20V/V input for the ringing signal.
• U1 pin 2, inverting input of external amplifier.
For multi layer boards, the traces connected to tip should not
cross the traces connected to ring. Since they will be
carrying high voltages, and could be subject to lightning or
surge depending on the application, using a larger than
minimum trace width is advised.
The 4-wire transmit and receive signal paths should not
cross. The receive path is any trace associated with the V_RX
input and the transmit path is any trace associated with V_TX
output. The physical distance between the two signal paths
should be maximized to reduce crosstalk.
The mode control signals and detector outputs should be
routed away from the analog circuitry. Though the digital
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