HC55171B Datasheet, PDF (7/11 Pages) Intersil Corporation – Low Cost 5 REN Ringing SLIC for ISDN Modem/TA and WL

HC55171B
TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR
V_BAT = -65V
R_TRAP
CF
RMS R_TRAP
CF
RMS
0Ω
1.10
52.5 1330Ω 1.25
45.9
660Ω
1.15
49.8 1600Ω 1.30
44.1
1040Ω 1.20
47.8 1800Ω 1.35
42.5
TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR
V_BAT = -60V
R_TRAP
CF
RMS R_TRAP
CF
RMS
0Ω
1.10
48.2 1460Ω 1.25
42.0
740Ω
1.15
45.6 1760Ω 1.30
40.4
1129Ω 1.20
43.7 2030Ω 1.35
38.8
The voltages listed in the tables are driven from a logic
source that will not drive the ringing input negative. If the
ringing input is driven negative by 200mV, the peak-to-peak
ringing amplitudes can be increased.
Ringing Voltage Limiting Factors
As the load impedance decreases (increasing REN), the
source impedance of the SLIC during ringing slightly
attenuates the ringing signal.
If additional surge protection resistance must be used with
the trapezoidal circuit, the loop length performance of the
circuit will decrease proportionally to the added resistance
in the Tip and Ring leads. For example if 30Ω protection
resistors is used in each of the Tip and Ring leads, the
ringing loop length will decrease by a total of 60Ω.
Low Level Ringing Interface
The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.
Loop Detector Interface
The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set-
ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 1.
SLIC Operating State During Ringing
The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector
interface). Figure 2 shows the control interface for the dual
detector interface and the single detector interface.
HC55171B
ADDITIONAL PULL UP RESISTOR
NU 23
RDI 20
RDO 21
V_RING 24
V_CC
D_TRAP
R_TRAP
C_TRAP
V_RING
FIGURE 1. APPLICATION CIRCUIT WIRING FOR SINGLE
LOOP DETECTOR INTERFACE
(DUAL DETECTOR INTERFACE)
MODE ACTIVE
(LOGIC HI)
F1 _{(LOGIC HI)}
F0
RINGING
V_RING
VALID DET
SHD
RTD
ACTIVE
SHD
(SINGLE DETECTOR INTERFACE)
MODE ACTIVE
(LOGIC HI)
RINGING
F1 _{(LOGIC HI)}
F0
V_RING
VALID DET
SHD
SHD
ACTIVE
SHD
FIGURE 2. DETECTOR LOGIC INTERFACES
Additional Application Information
Transhybrid Balance
Since the receive signal and its echo are 180 degrees out of
phase, the summing node of an operational amplifier can be
used to cancel the echo. Nearly all CODECs have an inter-
nal amplifier for echo cancellation. The circuit in Figure 3
shows the cancellation amplifier circuit.
R_A
R_F
V_RX
R_B
V_OUT1
-
+
VO
FIGURE 3. TRANSHYBRID AMPLIFIER CIRCUIT
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