CD4536BMS Datasheet, PDF (7/13 Pages) Intersil Corporation – CMOS Programmable Timer

CD4536BMS
Logic Diagram (Continued)
A
B
p
n
p
C
n
D
E
F
R
Q
CLDIS
CL Q
FF9
R
DQ
CL Q
FF10
R
φQ
φQ
FF11
R
φQ
φQ
FF16
R
φ^Q
φ_Q
FF17
R
φQ
φQ
FF18
R
φQ
φQ
FF24
9A _*
10
B
*
11
C
*
12D *
15 _*
MONO IN
G
1 OF 16 DECODER (TRANSMISSION-GATE TREE LOGIC)
VSS
N
P
DECODE
13 ^OUT
DETAIL FOR
FF3-8, 11-16, 17-24
DETAIL FOR
FF1, FF2, FF10, FF9, FF25
CLEN (CLDIS FOR FF9 AND FF25)
φQ
VDD
φ _RQ
Q
p
e
φR
Q
S
φ
R
N
P
n
p
D
b
f
a
p
n
φ
p
c
d
c
Q
n
φ
P
φ
P
N
φ
N
φ
φ
P
f
Q
n
φ
p
φ
b
a
n
p
d
n
p
n
P
N
φ
Q
N
CL
e
φ
φ
R
R
φ
φ
P ^{φ pn φ}
R
R
R
R
N
N
R
CLEN
CL Q
Q
FF1
D
Q
CL Q
FF2, 10
CLDIS Q
CL Q
FF9
CLDIS Q
CL _S Q
FF25
N
φ
VSS
FF1: AS SHOWN EXCEPT Q NOT BROUGHT OUT
FF9: SAME AS FF1 EXCEPT Q IS BROUGHT OUT AND Q, Q GO TO TGf AND TGe RESP.
FF2, FF10: DELETE TGe, TGf, AND INVf; FEED Q TO D; DELETE CLEN, CLDIS
FF25: INVa AND INVd BECOME 2-INPUT NAND GATES, WITH ADDED INPUTS S; FEED Q
TO TGf VSS TO TGe PREVIOUS Q INPUT; DELETE Q OUTPUT
FIGURE 1. (Continued)
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